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Paul Mackerras
d4f51e08c8
This adds logic to detect the cases where the quotient of the division overflows the range of the output representation, and return all zeroes in those cases, which is what POWER9 does. To do this, we extend the dividend register by 1 bit and we do an extra step in the division process to get a 2^64 bit of the quotient, which ends up in the 'overflow' signal. This catches all the cases where dividend >= 2^64 * divisor, including the case where divisor = 0, and the divde/divdeu cases where |RA| >= |RB|. Then, in the output stage, we also check that the result fits in the representable range, which depends on whether the division is a signed division or not, and whether it is a 32-bit or 64-bit division. If dividend >= 2^64 or the result doesn't fit in the representable range, write_data is set to 0 and write_cr_data to 0x20000000 (i.e. cr0.eq = 1). POWER9 sets the top 32 bits of the result to zero for 32-bit signed divisions, and sets CR0 when RC=1 according to the 64-bit value (i.e. CR0.LT is always 0 for 32-bit signed divisions, even if the 32-bit result is negative). However, modsw with a negative result sets the top 32 bits to all 1s. We follow suit. This updates divider_tb to check the invalid cases as well as the valid case. This also fixes a small bug where the reset signal for the divider was driven from rst when it should have been driven from core_rst. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
5 years ago | |
|---|---|---|
| fpga | 5 years ago | |
| hello_world | ||
| media | 5 years ago | |
| scripts | 5 years ago | |
| sim-unisim | ||
| tests | ||
| .gitignore | 5 years ago | |
| .travis.yml | ||
| LICENSE | ||
| Makefile | 5 years ago | |
| README.md | 5 years ago | |
| cache_ram.vhdl | 5 years ago | |
| common.vhdl | 5 years ago | |
| core.vhdl | 5 years ago | |
| core_debug.vhdl | 5 years ago | |
| core_tb.vhdl | 5 years ago | |
| countzero.vhdl | 5 years ago | |
| cr_file.vhdl | ||
| crhelpers.vhdl | ||
| decode1.vhdl | 5 years ago | |
| decode2.vhdl | 5 years ago | |
| decode_types.vhdl | 5 years ago | |
| divider.vhdl | 5 years ago | |
| divider_tb.vhdl | 5 years ago | |
| dmi_dtm_dummy.vhdl | 5 years ago | |
| dmi_dtm_tb.vhdl | ||
| dmi_dtm_xilinx.vhdl | 5 years ago | |
| execute1.vhdl | 5 years ago | |
| execute2.vhdl | ||
| fetch1.vhdl | 5 years ago | |
| fetch2.vhdl | 5 years ago | |
| glibc_random.vhdl | ||
| glibc_random_helpers.vhdl | ||
| helpers.vhdl | ||
| icache.vhdl | 5 years ago | |
| icache_tb.vhdl | 5 years ago | |
| insn_helpers.vhdl | 5 years ago | |
| loadstore1.vhdl | ||
| loadstore2.vhdl | 5 years ago | |
| logical.vhdl | 5 years ago | |
| microwatt.core | 5 years ago | |
| multiply.vhdl | 5 years ago | |
| multiply_tb.vhdl | ||
| plru.vhdl | 5 years ago | |
| plru_tb.vhdl | 5 years ago | |
| ppc_fx_insns.vhdl | 5 years ago | |
| register_file.vhdl | 5 years ago | |
| rotator.vhdl | 5 years ago | |
| rotator_tb.vhdl | 5 years ago | |
| sim_console.vhdl | ||
| sim_console_c.c | ||
| sim_jtag.vhdl | 5 years ago | |
| sim_jtag_socket.vhdl | 5 years ago | |
| sim_jtag_socket_c.c | 5 years ago | |
| sim_uart.vhdl | ||
| simple_ram_behavioural.vhdl | ||
| simple_ram_behavioural_helpers.vhdl | ||
| simple_ram_behavioural_helpers_c.c | ||
| simple_ram_behavioural_tb.bin | ||
| simple_ram_behavioural_tb.vhdl | ||
| soc.vhdl | 5 years ago | |
| wishbone_arbiter.vhdl | ||
| wishbone_debug_master.vhdl | ||
| wishbone_types.vhdl | ||
| writeback.vhdl | 5 years ago | |
README.md
Microwatt
A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.
Simulation using ghdl
- Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../
- Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
- Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin
- Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null
Synthesis on Xilinx FPGAs using Vivado
-
Install Vivado (I'm using the free 2019.1 webpack edition).
-
Setup Vivado paths:
source /opt/Xilinx/Vivado/2019.1/settings64.sh
- Install FuseSoC:
pip3 install --user -U fusesoc
- Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
- Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):
fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
- To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt
Testing
- A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check
Issues
This is functional, but very simple. We still have quite a lot to do:
- There are a few instructions still to be implemented
- Need to add caches and bypassing (in progress)
- Need to add supervisor state (in progress)