69 Commits (ae76adefbf2f1129eca4d81b032573efa0434977)
 

Author SHA1 Message Date
Jean-François Nguyen ae76adefbf Add checks for Byte-Reverse instructions. 2 years ago
Jean-François Nguyen 4bf2398208 Add checks for BCD Assist instructions. 2 years ago
Jean-François Nguyen 23dcd80a9e Add checks for Rotate/Shift instructions. 2 years ago
Jean-François Nguyen aeed09092c Add checks for logical instructions. 2 years ago
Jean-François Nguyen 373a4e28b6 pfv.Interface: add support for skipping instructions.
The `pfv.skip` signal is used to handle cases where the DUT does not
actually execute an instruction (e.g. a no-op), which may prevent some
side-effects (e.g. GPR accesses) from being observable.
2 years ago
Jean-François Nguyen bce3205759 insn.spec.branch: remove duplicate read of MSR.SF. 2 years ago
Jean-François Nguyen 57e29666ce cores/microwatt: fix CLI instructions. 2 years ago
Jean-François Nguyen 0f731db18a Add checks for Load/Store instructions. 2 years ago
Jean-François Nguyen 5ca0001b4b Add data storage check.
This check is implemented in two parts:
- an implementation-dependant DataStorageModel, which is connected to
  the DUT and emulates bus accesses to a r/w memory.
- a DataStorageTestbench, which checks that a load from a given address
  returns the last value that was stored to it.
2 years ago
Jean-François Nguyen 5d21832c57 pfv.Interface: simplify memory port.
The former `pfv.insn_mem` field was redundant with `pfv.insn` and
`pfv.cia`.

Also, validate memory port properties in InsnTestbench.
2 years ago
Jean-François Nguyen fec1b838d5 check: add --cover argument to use SymbiYosys in coverage mode. 2 years ago
Jean-François Nguyen ec7cfdd719 cores/microwatt: move microwatt.py to its own python module.
Also:
* update dependencies.
* add amaranth-soc as a dependency, in order to reuse its bus
  interfaces (e.g. Wishbone).
* add a `prog` argument to PowerFVSession that overrides the name of
  its CLI.
2 years ago
Jean-François Nguyen a5e69954a4 Add checks for MTMSR/MFMSR instructions. 2 years ago
Jean-François Nguyen dd6048f14b In-depth refactoring, improved user interface.
* A PowerFVSession class provides a REPL interface. Functionality is
  split into commands (e.g. add checks, build) which can be provided
  interactively or from a file.

  See cores/microwatt for an example of its integration.

* Instruction specifications are now separated from verification
  testbenches.

  An InsnSpec class provides a behavioral model using the same PowerFV
  interface as a core. This interface is output-only for a core, but
  bidirectional for the InsnSpec:
    - fields related to context (e.g. read data) are inputs,
    - fields related to side-effects (e.g. write strobes) are outputs.

  The testbench is responsible for driving inputs to the same values
  as the core, then check outputs for equivalence. This decoupling
  provides a path towards using PowerFV in simulation.

* Instruction encodings are now defined by their fields, not their
  format (which was problematic e.g. X-form has dozens of variants).

  Field declarations can be preset to a value, or left undefined. In
  the latter case, they are implicitly cast to AnyConst (which is
  useful for arbitrary values like immediates).
2 years ago
Jean-François Nguyen 05965592f9 checks.insn._addsub: fix incorrect ADDEX updates to OV/OV32. 2 years ago
Jean-François Nguyen 951ca2cdfb cores/microwatt: add checks for add/subtract instructions. 2 years ago
Jean-François Nguyen f06c8000b0 checks.insn: add checks for add/subtract instructions. 2 years ago
Jean-François Nguyen baaac86be1 cores/microwatt: add checks for MTSPR and MFSPR instructions. 2 years ago
Jean-François Nguyen 8cf56ab5dc checks.insn: add checks for MTSPR and MFSPR instructions. 2 years ago
Jean-François Nguyen 21be78c4f8 cores/microwatt: add checks for compare instructions. 2 years ago
Jean-François Nguyen 692e8ec7c4 checks.insn: add checks for compare instructions. 2 years ago
Jean-François Nguyen a413025fcb Update SPR interface and split consistency check.
* Use bitmasks to describe SPR accesses at the field granularity.

* Use separate checks for each SPR, instead of covering them all at
  once. Users may run them in the same batch, and know which SPR passes
  or fails its check.
2 years ago
Jean-François Nguyen e3f4bf6e24 cores/microwatt: add check for MCRF instruction. 2 years ago
Jean-François Nguyen 2ffff6196b checks.insn: add check for MCRF instruction. 2 years ago
Jean-François Nguyen 4c16035a70 checks.insn._cr: fix order of spec_cr_w_data bits. 2 years ago
Jean-François Nguyen 010c383ed7 tb: remove testbench start trigger.
We don't use it currently; we just assume the sync domain is under
reset at the beginning of the BMC.

Also, fix a regression in the cycle counter introduced by 9ea58a47.
2 years ago
Jean-François Nguyen 2c0b22b96c cores/microwatt: add checks for CR logical instructions. 2 years ago
Jean-François Nguyen fee59d2257 checks.insn: add checks for CR logical instructions. 2 years ago
Jean-François Nguyen bc06e67fe8 checks.insn._branch: add missing PowerFVCheck name. 2 years ago
Jean-François Nguyen 9ea58a47a9 Refactor to facilitate integration with CLIs and config files.
* Checks are now split in two modules: checks.cons for consistency
  checks, checks.insn for instructions.

* Checks are derived from PowerFVCheck and have a shorthand (e.g.
  "insn_b"). PowerFVCheck holds a mapping between its subclasses and
  their shorthands.

* Instruction checks definitions have been simplified to one-liners,
  and grouped into a single file.

* A Trigger class has been added to define testbench triggers.
2 years ago
Jean-François Nguyen 5c097b9474 checks._branch: fix branches to LR/CTR/TAR.
- remove check for undefined mnemonics (afaiu, their BO value isn't illegal).
- add check for illegal bcctr/bcctrl forms (with BO(2) = 0).
- fix target offset for branches to LR/CTR/TAR.
- use MSR.SF to check the upper bits of target addresses.
2 years ago
Jean-François Nguyen 5649f60c78 checks.insn_bcctrl: fix typo. 2 years ago
Jean-François Nguyen e9d7a91e01 utils: add helper to mask addresses according to MSR.SF. 2 years ago
Jean-François Nguyen d9ed524cb3 powerv.insn: fix width of XO width for XL-form insns. 2 years ago
Jean-François Nguyen 0ca97a8d6a checks.{cr,gpr}: add support for interrupts.
Also, rephrase gpr.Check docstring.
2 years ago
Jean-François Nguyen 25500cd680 checks.spr: refactor. 2 years ago
Jean-François Nguyen bc13b27212 cores/microwatt: expose MSR and SRR0/SRR1. 2 years ago
Jean-François Nguyen c6a74333e8 pfv: add MSR and SRR0/SRR1 SPRs. 2 years ago
Jean-François Nguyen 58bef1a741 checks: add checks for branch instructions. 3 years ago
Jean-François Nguyen 5c9bc3e68c cores/microwatt: add support for concurrent execution of formal checks. 3 years ago
Jean-François Nguyen 6ae4978f0c pfv: expose CR as a flat 32-bit value. 3 years ago
Jean-François Nguyen ed2122d940 cores/microwatt: add support for SPRCheck. 3 years ago
Jean-François Nguyen 2988ffc617 checks.spr: add SPRCheck. 3 years ago
Jean-François Nguyen ca66e3a45e cores/microwatt: add support for CRCheck. 3 years ago
Jean-François Nguyen e7e9bb08f0 checks.cr: add CRCheck. 3 years ago
Jean-François Nguyen 5076bdb9eb cores/microwatt: add support for GPRCheck. 3 years ago
Jean-François Nguyen b84a23877a checks.gpr: add GPRCheck. 3 years ago
Jean-François Nguyen 6b5536eb0f tb: fix error message. 3 years ago
Jean-François Nguyen 6922b4bd53 cores/microwatt: add support for IAForwardCheck.
Also, use non-default cache sizes for faster verification.
3 years ago
Jean-François Nguyen e0e434204b checks.ia_fwd: add check. 3 years ago