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fpu-init
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core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
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jtag-port-2
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720 Commits (2081bdaa27d3422afdde3972d118819e55e3883f)
 

Author SHA1 Message Date
Anton Blanchard 1aadee281d
Merge pull request #6 from mikey/gif 
Add pretty gif demo of MicroPython on Microwatt to README.md
 5 years ago
Anton Blanchard 96787091a6 Add -Wall to CFLAGS 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Michael Neuling d618171d13 Add pretty gif demo of MicroPython on Microwatt to README.md 
Signed-off-by: Michael Neuling <mikey@neuling.org>
 5 years ago
Anton Blanchard 7277c6b5ab Add missing argument to fprintf warning 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 77f1588a7f Add some initial FPGA synthesis instructions 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 0a0ad9b384 Rebuild hello world assuming a 50MHz clock 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard c036363d8f
Merge pull request #3 from olofk/plle2 
Add and use plle2 primitive for nexys boards
 5 years ago
Olof Kindgren 12327034d6 Add and use plle2 primitive for nexys boards 5 years ago
Anton Blanchard 5b2984a15d
Merge pull request #4 from sharkcz/build 
don't cross compile when on Power
 5 years ago
Dan Horák 2d7994dc12 don't cross compile when on Power 5 years ago
Anton Blanchard 8bc3e8ea0a Add a simple hello_world example that also echos input 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 01e6b8f583
Merge pull request #2 from olofk/fusesoc_nexys_a7 
Fusesoc nexys a7
 5 years ago
Olof Kindgren b9bf19f912 Added synthesis target 
The synth target can be used to analyze the core after synthesis
without running P&R. Currently, the only edalize backends that
support synthesis without P&R are vivado and icestorm, and icestorm
needs yosys built with verific support to parse vhdl.

To run synthesis only for a part, run

fusesoc run --target=synth --tool=vivado microwatt --part=<part>

where part is a valid Xilinx part such as xc7a100tcsg324-1
 5 years ago
Olof Kindgren 250d09ed2d Add Nexys Video support 5 years ago
Olof Kindgren 5e56b14125 Add FuseSoC core description file with Nexys A7 support 5 years ago
Olof Kindgren abca85b034 Add constraint file for Nexys A7 5 years ago
Olof Kindgren e8ad9bed10 Expose ram init file and memory size through toplevel 5 years ago
Olof Kindgren b5bccc4c13 Add dummy clock generator 5 years ago
Anton Blanchard 37fe8b954c Add a few more FPGA related files 
Add a temporary gcc patch to remove hardware divide instructions.

Also add a firmware.hex file built with a gcc with the above patch.

Right now micropython assumes 1MB of BRAM, which limits the FPGAs
we can run on. We should be able to cut it down somewhat.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago