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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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17 Commits (f384f504a1a97317f5697d3ad6c91240940642d4)

Author SHA1 Message Date
Anton Blanchard 270d7b1b9a Cmod A7-35 support 
This adds support for the Digilane Cmod A7-35.

I had to use the MMCM because the clock (12 MHz) is below the PLL
minimum of 19 MHz.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 14da542d4a
Merge pull request #20 from antonblanchard/reset-rework2 
Rework reset code
 5 years ago
Anton Blanchard 63295526ad Add CONFIG_VOLTAGE and CFGBVS entries 
Remove a couple of warnings from Vivado.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 03fd06deaf Rework SOC reset 
The old reset code was overly complicated and never worked properly.
Replace it with a simpler sequence that uses a couple of shift registers
to assert resets:

- Wait a number of external clock cycles before removing reset from
  the PLL.

- After the PLL locks and the external reset button isn't pressed,
  wait a number of PLL clock cycles before removing reset from the SOC.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard a53ad60014 Rename a few reset signals 
clk -> ext_clk
reset_n -> ext_rst
reset -> rst

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 5379b805ec Arty A7 reset pin is C2 
Use C2 for reset, and fix up a few whitespace issues.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
riktw 4ebd6fc1f7 Added support for building for Arty A7 boards 5 years ago
Anton Blanchard 95b9f19882 Fix ghdl build error with pp_soc_memory 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 1fa0b332ca micropython only requires 512kB of BRAM 
Mikey points out that our stack grows down from 512kB and our
heap is below that too, so we can reduce our BRAM requirements,
which allowing some smaller FPGA boards to work. Not sure why
I thought we were using memory between 512kB and 1MB.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 0a0ad9b384 Rebuild hello world assuming a 50MHz clock 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Olof Kindgren 12327034d6 Add and use plle2 primitive for nexys boards 5 years ago
Anton Blanchard 8bc3e8ea0a Add a simple hello_world example that also echos input 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Olof Kindgren abca85b034 Add constraint file for Nexys A7 5 years ago
Olof Kindgren e8ad9bed10 Expose ram init file and memory size through toplevel 5 years ago
Olof Kindgren b5bccc4c13 Add dummy clock generator 5 years ago
Anton Blanchard 37fe8b954c Add a few more FPGA related files 
Add a temporary gcc patch to remove hardware divide instructions.

Also add a firmware.hex file built with a gcc with the above patch.

Right now micropython assumes 1MB of BRAM, which limits the FPGAs
we can run on. We should be able to cut it down somewhat.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago