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microwatt
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  • c9e92483b8 decode: Push mtspr/mfspr register decoding down into execute1 Paul Mackerras 2019-09-28 14:43:46 +1000
  • 3e6f656a90 Add MCRF instruction Benjamin Herrenschmidt 2019-09-25 00:09:35 +1000
  • 554ae88540 Implement absolute branches Benjamin Herrenschmidt 2019-09-24 15:47:25 +1000
  • 4174cd8e93
         Merge pull request #77 from antonblanchard/timing Anton Blanchard 2019-09-30 18:21:54 +1000
  • 4a9a9df4dd
         Merge pull request #76 from antonblanchard/misc Anton Blanchard 2019-09-30 18:00:41 +1000
  • 9961d70dfb Improve PLL/MMCM clocks configuration Benjamin Herrenschmidt 2019-09-24 14:57:34 +1000
  • 5f28109957 Don't reset JTAG request register asynchronously Benjamin Herrenschmidt 2019-09-26 11:09:46 +1000
  • 48e6e719d3 Multiply needs to be 16 stages to fix all timing issues Benjamin Herrenschmidt 2019-09-26 10:53:55 +1000
  • 9789d258fb loadstore2: Do data formatting after a register stage Paul Mackerras 2019-09-25 20:27:08 +1000
  • 492bf06740 corefile: Remove duplicate wishbone_debug_master Benjamin Herrenschmidt 2019-09-30 13:54:04 +1000
  • ab5c6ab9ac fpga: Arty A7's don't need multiple filesets Benjamin Herrenschmidt 2019-09-30 12:56:09 +1000
  • 80a0e7fcf3 execute1: simplify flush_out Benjamin Herrenschmidt 2019-09-25 16:42:44 +1000
  • 8b55fc4d9e Reformat fetch2 Benjamin Herrenschmidt 2019-09-25 11:28:20 +1000
  • 41a4eb8271 Move fetch2 <-> icache definitions Benjamin Herrenschmidt 2019-09-25 11:26:36 +1000
  • 79b64baefc Remove unused pipe_stop in Fetch1ToFetch2Type Benjamin Herrenschmidt 2019-09-25 12:48:15 +1000
  • 79b0b9a046 Fix PLL reset signal name in toplevel Benjamin Herrenschmidt 2019-09-11 12:18:22 +0100
  • 8af2b004c3 Simplify fetch1 Benjamin Herrenschmidt 2019-09-24 12:17:42 +1000
  • 3a6fcc09d4 Reformat fetch1 Benjamin Herrenschmidt 2019-09-24 12:11:24 +1000
  • 586abb70a0 Update dependency Benjamin Herrenschmidt 2019-09-25 16:54:25 +1000
  • feb8ee7149
         Merge pull request #75 from paulusmack/master Anton Blanchard 2019-09-28 14:32:31 +1000
  • 555802d996
         Merge pull request #74 from paulusmack/divider Anton Blanchard 2019-09-28 14:32:14 +1000
  • 1158c81500 fpga: Add definitions for Arty A7-100 board Paul Mackerras 2019-09-28 09:08:13 +1000
  • 25b9450475 divider: Do absolute-value ops in divider instead of decode Paul Mackerras 2019-09-28 08:55:08 +1000
  • e6536d4b8b divider: Always compute result/sresult/d_out.write_reg_data Paul Mackerras 2019-09-25 20:03:46 +1000
  • ad040601e6
         Merge pull request #73 from antonblanchard/remove-divide-patch Anton Blanchard 2019-09-25 09:13:18 +1000
  • c8328cdf84 Remove gcc software divide patch Anton Blanchard 2019-09-25 08:03:10 +1000
  • 82fe8dc6e2
         Merge pull request #72 from antonblanchard/build-error Anton Blanchard 2019-09-24 20:54:28 +1000
  • a9e5fe78fb
         Merge pull request #71 from antonblanchard/dependencies Anton Blanchard 2019-09-24 20:34:52 +1000
  • 8102e7863b Fix build issue in dmi_dtm_dummy.vhdl Anton Blanchard 2019-09-24 20:27:34 +1000
  • 26f70264b3 Update Makefile dependencies Anton Blanchard 2019-09-24 17:50:17 +1000
  • b57325ce29 Merge branch 'divider' of https://github.com/paulusmack/microwatt Anton Blanchard 2019-09-24 17:33:21 +1000
  • cd4da50650
         Merge pull request #70 from antonblanchard/badly-named-carry Anton Blanchard 2019-09-24 17:25:44 +1000
  • 5a6f8d26d1 Rename OP_SUBFC -> OP_SUBFE, OP_ADDC -> OP_ADDE Anton Blanchard 2019-09-24 16:55:09 +1000
  • ba783fddd5
         Merge pull request #69 from antonblanchard/debug-module Anton Blanchard 2019-09-24 16:51:03 +1000
  • 6cae10eebd Terminate test on illegal instruction Anton Blanchard 2019-09-23 21:22:18 +1000
  • 8c5dcc8c4c Fix ghdl error Anton Blanchard 2019-09-23 21:20:12 +1000
  • d82f4c18b6 Add core_debug.vhdl to fusesoc configs Anton Blanchard 2019-09-23 20:49:21 +1000
  • a01ffaeb64 Speed up the divider a little Paul Mackerras 2019-09-23 14:39:50 +1000
  • d5bc6c8824 Add a divider unit and a testbench for it Paul Mackerras 2019-09-22 17:24:14 +1000
  • 42d802bed0 Add distclean to Makefile Benjamin Herrenschmidt 2019-09-20 16:45:26 +1000
  • fe275effeb New C based JTAG debug tool Benjamin Herrenschmidt 2019-09-16 16:29:08 +0100
  • 98f0994698 Add core debug module Benjamin Herrenschmidt 2019-09-10 17:43:52 +0100
  • 554b753172 Add jtag support in simulation via a socket Benjamin Herrenschmidt 2019-09-16 16:28:48 +0100
  • ad14a41d80 Add DMI address decoder Benjamin Herrenschmidt 2019-09-10 17:39:59 +0100
  • b46f81fae4 Wishbone debug module Benjamin Herrenschmidt 2019-09-10 17:31:25 +0100
  • ee52fd4d80 Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs Benjamin Herrenschmidt 2019-09-10 17:17:59 +0100
  • 1206dfe18c Use a 3 way WB arbiter and cleanup fpga toplevel Benjamin Herrenschmidt 2019-09-10 17:03:37 +0100
  • 6571b13308
         Merge pull request #66 from antonblanchard/reformat-4 Anton Blanchard 2019-09-19 22:49:41 +1000
  • 7e7010c304 Reformat crhelpers, and remove some stale code Anton Blanchard 2019-09-19 21:53:27 +1000
  • ae42370d24 Reformat helpers Anton Blanchard 2019-09-19 21:53:09 +1000
  • 9ff86a62f5 Reformat insn_helpers Anton Blanchard 2019-09-19 21:52:07 +1000
  • c5d327cebf
         Merge pull request #65 from antonblanchard/loadstore-opt Anton Blanchard 2019-09-19 21:48:22 +1000
  • 687051ecbb Reformat loadstore1 Anton Blanchard 2019-09-19 21:37:43 +1000
  • 6e442e07a5 Reformat loadstore2 Anton Blanchard 2019-09-19 21:36:51 +1000
  • e1a71e4545 loads don't do both byte reversal and sign extension Anton Blanchard 2019-09-19 21:31:34 +1000
  • 4df05e0598
         Merge pull request #64 from antonblanchard/reformat-3 Anton Blanchard 2019-09-19 21:07:31 +1000
  • 48f4dcece8
         Merge pull request #63 from antonblanchard/multiply-cleanup Anton Blanchard 2019-09-19 20:36:26 +1000
  • df1165bdfc Reformat wishbone code Anton Blanchard 2019-09-19 20:35:42 +1000
  • 06392e7eaa Reformat glibc_random Anton Blanchard 2019-09-19 20:33:58 +1000
  • 1d5e8c2eb4 Reformat simple_ram_behavioural Anton Blanchard 2019-09-19 20:32:07 +1000
  • fd9e971b2c Reformat sim_console Anton Blanchard 2019-09-19 20:28:37 +1000
  • 28e6d343dc Reformat multiply_tb Anton Blanchard 2019-09-19 20:26:55 +1000
  • fc10935797 Reformat execute2 Anton Blanchard 2019-09-19 20:24:29 +1000
  • 4d0afa3a6d Reformat CR file Anton Blanchard 2019-09-19 20:22:36 +1000
  • 4d9b2a1165 Reformat register file Anton Blanchard 2019-09-19 20:21:58 +1000
  • 8dd97fbe7f Reformat multiply code Anton Blanchard 2019-09-19 20:19:46 +1000
  • 99dd4de54e Don't use VHDL 2008 condition operator in multiply Anton Blanchard 2019-09-19 20:18:01 +1000
  • 550b2b8608
         Merge pull request #62 from antonblanchard/byte-reverse-store-opt Anton Blanchard 2019-09-16 13:17:37 +1000
  • 135805d2ac
         Merge pull request #61 from antonblanchard/execute-cleanup Anton Blanchard 2019-09-16 13:14:25 +1000
  • a061924a78 Move byte reversal of stores to first cycle Anton Blanchard 2019-09-16 11:49:44 +1000
  • 6d85920068 execute1 no longer needs sim_console Anton Blanchard 2019-09-16 11:18:53 +1000
  • a4c8dd860a
         Merge pull request #60 from antonblanchard/testbenches Anton Blanchard 2019-09-15 22:52:14 +1000
  • 1b6eef2a5d Fix multiply_tb Anton Blanchard 2019-09-13 20:35:08 +1000
  • 1e3e16e500 Add an icache testbench Anton Blanchard 2019-09-13 20:17:17 +1000
  • d573748da0
         Merge pull request #56 from antonblanchard/writeback-fix3 Anton Blanchard 2019-09-15 22:08:57 +1000
  • 152261fac8 Remove cycle in writeback Anton Blanchard 2019-09-15 18:03:48 +1000
  • 7bb88d5321
         Merge pull request #59 from antonblanchard/trap-decode Anton Blanchard 2019-09-15 21:37:47 +1000
  • f5a5b91736
         Merge pull request #58 from antonblanchard/decode2-assert Anton Blanchard 2019-09-15 21:30:30 +1000
  • 427effdaa9 Fix make check Anton Blanchard 2019-09-15 21:21:36 +1000
  • d813ffb748 Fix spurious outstanding assert Anton Blanchard 2019-09-15 18:59:24 +1000
  • 30aa16d8f3
         Merge pull request #57 from antonblanchard/add-nop Anton Blanchard 2019-09-15 18:34:27 +1000
  • 9867fb6149 Add a decode for the nop instruction Anton Blanchard 2019-09-15 18:18:24 +1000
  • 85062793b1
         Merge pull request #55 from antonblanchard/fetch-fix Anton Blanchard 2019-09-15 11:18:42 +1000
  • d52046104f Add a default value for RESET_ADDRESS Anton Blanchard 2019-09-15 10:25:57 +1000
  • 71e45a82ee
         Merge pull request #51 from antonblanchard/writeback-fix Anton Blanchard 2019-09-15 09:55:10 +1000
  • e69e79d8af Reformat writeback.vhdl Anton Blanchard 2019-09-15 09:07:34 +1000
  • 50a361a5dc Exit if we try to write more than one GPR or CR in a cycle Anton Blanchard 2019-09-15 09:04:47 +1000
  • ab34c48392
         Merge pull request #50 from antonblanchard/decode1-opt Anton Blanchard 2019-09-12 21:15:24 +1000
  • acdb2ea157 No need to gate nia or insn in decode1 Anton Blanchard 2019-09-12 17:06:09 +1000
  • 986881f258 Add a patch to route the NIA out to GPIOs nia-debug Anton Blanchard 2019-09-11 15:43:49 +1000
  • 0e6861e5db
         Merge pull request #49 from antonblanchard/icache-2 Anton Blanchard 2019-09-12 16:14:28 +1000
  • 89849a6856 Add a simple direct mapped icache Anton Blanchard 2019-09-11 13:05:17 +1000
  • 6cbf456388 SOC memory wishbone should clear ACK regardless of STB Anton Blanchard 2019-09-11 17:21:52 +1000
  • 67446709ca
         Merge pull request #48 from antonblanchard/clk_gen_bypass Anton Blanchard 2019-09-12 13:03:33 +1000
  • d89a9929fd Fix clk_gen_bypass Anton Blanchard 2019-09-12 12:25:18 +1000
  • 80aa781454
         Merge pull request #47 from antonblanchard/if-fix Anton Blanchard 2019-09-12 09:46:22 +1000
  • ca6f84efd6
         Merge pull request #46 from antonblanchard/record-fix Anton Blanchard 2019-09-12 09:46:01 +1000
  • b9e28598b4 Explicitly check against '1' in if statements Anton Blanchard 2019-09-12 09:19:31 +1000
  • 142a722ce4 Remove names from end record statements Anton Blanchard 2019-09-12 09:04:02 +1000
  • 43f81773b4
         Merge pull request #45 from antonblanchard/fixes Anton Blanchard 2019-09-11 22:53:47 +1000