Browse Source

testing full litex software build

master
openpowerwtf 3 months ago
parent
commit
20b16f1810
  1. 227
      build/litex/a2p_a2o_32.py
  2. 1
      build/litex/a2p_new/__init__.py
  3. 50
      build/litex/a2p_new/boot-helper.S
  4. 150
      build/litex/a2p_new/core.py
  5. 261
      build/litex/a2p_new/crt0.S
  6. 129
      build/litex/a2p_new/crtsavres.s
  7. 146
      build/litex/a2p_new/defines.s
  8. 18
      build/litex/a2p_new/irq.h
  9. 67
      build/litex/a2p_new/system.h
  10. 14250
      build/litex/a2p_new/verilog/A2P_WB.v
  11. 27
      build/litex/bin2init
  12. 14250
      sim/soc/A2P_WB.v
  13. 17887
      sim/soc/bios.s
  14. 6199
      sim/soc/cmod7_rom.init
  15. 52
      sim/soc/readme.md
  16. 1958
      sim/soc/soc.v
  17. 455
      sim/soc/tb_litex_soc.cpp
  18. 4
      sim/soc/unisims/BUFG.v
  19. 10
      sim/soc/unisims/DNA_PORT.v
  20. 21
      sim/soc/unisims/FD.v
  21. 24
      sim/soc/unisims/FDCE.v
  22. 24
      sim/soc/unisims/FDPE.v
  23. 10
      sim/soc/unisims/IDELAYCTRL.v
  24. 24
      sim/soc/unisims/IDELAYE2.v
  25. 13
      sim/soc/unisims/IOBUF.v
  26. 13
      sim/soc/unisims/IOBUFDS.v
  27. 31
      sim/soc/unisims/ISERDESE2.v
  28. 95
      sim/soc/unisims/MMCME2_ADV.v
  29. 12
      sim/soc/unisims/OBUFDS.v
  30. 33
      sim/soc/unisims/OSERDESE2.v
  31. 93
      sim/soc/unisims/XADC.v
  32. 1
      sim/soc/wbuart32

227
build/litex/a2p_a2o_32.py

@ -0,0 +1,227 @@ @@ -0,0 +1,227 @@
#!/usr/bin/python3

# A2P Test from A2O 32BE Test (minimal changes to see if litex software compile works with a2p)
# a2p_a2o_32.py --csr-csv csr.csv
# a2p_a2o_32.py --csr-csv csr.csv --build [--sys-clk-freq 50e6]
#

import os
import argparse

from migen import *

# wtf - use local platform
from platforms import cmod7
#from platforms import cmod7_kintex

# wtf - use local core (not built into litex)
# help python find package
# not needed anymore
#import sys
#binPath = os.path.dirname(os.path.realpath(__file__))
#sys.path.append(os.path.join(binPath, 'a2o')) # dir with core package; core.py defines core source location
# get core def
from a2p_new import A2P
# add to litex dict
from litex.soc.cores import cpu
cpu.CPUS['a2p'] = A2P

from litex.soc.cores.clock import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *

from litex.soc.cores.led import LedChaser
from litex.soc.cores import dna, xadc
from litex.soc.cores.gpio import GPIOIn
from litex.soc.cores.gpio import GPIOOut
from litex.soc.cores.bitbang import I2CMaster

from litex.soc.interconnect import wishbone

from litex.soc.cores import uart
from litex.soc.cores.uart import UART
from litex.soc.cores.uart import UARTPHY
from litex.soc.cores.uart import UARTWishboneBridge
from litescope import LiteScopeAnalyzer

# CRG ----------------------------------------------------------------------------------------------

class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()

self.submodules.pll = pll = S7MMCM(speedgrade=-1)
#wtf how do you add btn to reset sig?
#x = platform.request('user_btn',0)
self.comb += pll.reset.eq(self.rst)
#self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request('clk12'), 12e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.

self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)

def _to_signal(obj):
return obj.raw_bits() if isinstance(obj, Record) else obj

class BaseSoC(SoCCore):

def __init__(self, sys_clk_freq=int(50e6),
with_analyzer=False,
uart_baudrate=115200,
**kwargs):

coreUART = True
#romSize = 128*1024
#ramSize = 128*1024
romSize = 64 * 1024;
ramSize = 64 * 1024;
ddrSize = 16*1024*1024


# try build using different fpga's
platform = cmod7.Platform()
#platform = cmod7.Platform(fpga='xc7a200t-SBG484-1') # arty-200
#platform = cmod7_kintex.Platform(fpga='xc7k325t-ffv676-1 ) # kintex-325
#platform = cmod7_kintex.Platform(fpga='xc7k410t-ffv676-1') # kintex-410

SoCCore.__init__(self, platform, sys_clk_freq, csr_data_width=32,
#with_uart=coreUART, integrated_rom_size=romSize, integrated_sram_size=ramSize, don't set rom/ram if doing it below!!!!!
with_uart=coreUART, integrated_rom_size=0, integrated_sram_size=0,
ident='A2P', ident_version=True, uart_baudrate=uart_baudrate,
cpu_type='a2p', cpu_variant='WB')

print(f'Building variant={self.cpu.variant}.')

# no irq yet, but should be able to connect; need irq handler in crt0.s
self.add_constant('UART_POLLING')
# skip bios crc for sim
#self.add_constant('CONFIG_BIOS_NO_CRC') # doesnt work?
#self.add_config("BIOS_NO_CRC") # doesnt work?
#had to -DCONFIG_BIOS_NO_CRC=1 in GCC_FLAGS

# this appears to be how to set up fixed csr order but not sure it works this way. https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/soc_linux.py
#SoCCore.csr_map
#self.csr_map = {**SoCCore.csr_map, **{
#self.csr_map = {
# 'ctrl': 0,
# 'dna' : 1,
# 'uart': 2,
# 'i2c': 3,
# 'leds': 4
#}}
#interrupt_map = {**soc_cls.interrupt_map, **{
# 'uart': 0,
# 'timer0': 1,
#}}
self.mem_map = {
'rom': 0x00000000,
'ram': 0x00010000,
'main_ram': 0x01000000,
'csr': 0xFFF00000
}

# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

if not coreUART:
self.submodules.serial_bridge = UARTWishboneBridge(platform.request('serial'), sys_clk_freq)
self.add_wb_master(self.serial_bridge.wishbone)

self.add_csr('node_ctl')
self.add_csr('node_config')
self.add_csr('node_status')

# ON-BOARD MEM ------------------------------------------------------------------------------

with open('rom.init', 'r') as file:
hexdata = file.read().replace('\n', '')

#a2o how will this work for a2o? should allow 32BE or 64LE to load kernel+bios
# 1. core resets to 32BE
# 2. probably want to link kernel+bios in same mode, so have kernel deal with possible mode switch
# 3. load mem here in proper mode based on variant (A2O_32BE or A2O64_LE)

outFile = open('mem_init', 'w') # write data immediately so available even if not building (sim)
# this seems to work (specified in BE in rom.init, instructions are decoded properly)
# BUT, vivado wants each line to be 4B to match width (at least for sim)
bytedata = []
for i in range(0, len(hexdata), 8):
data = int(hexdata[i+6:i+8] + hexdata[i+4:i+6] + hexdata[i+2:i+4] + hexdata[i:i+2], 16) # BE->LE
bytedata.append(data)
outFile.write(hexdata[i+6:i+8] + hexdata[i+4:i+6] + hexdata[i+2:i+4] + hexdata[i:i+2] + '\n')
#bytedata.append(int(hexdata[i:i+2] + hexdata[i+2:i+4] + hexdata[i+4:i+6] + hexdata[i+6:i+8], 16))
romdata = bytedata
print('Read ' + str(len(romdata)) + ' bytes for ROM data.')
outFile.close()
print('Wrote mem.init')

self.add_rom('rom', origin=self.mem_map['rom'], size=romSize, contents=romdata) # name, origin, size, contents=[], mode='r'
# make this sram to match what linker expects
self.add_ram('sram', origin=self.mem_map['ram'], size=ramSize) # name, origin, size, contents=[], mode='rw'

# External Mem -----------------------------------------------------------------------------
self.add_ram('main_ram', origin=self.mem_map['main_ram'], size=ddrSize)

# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all('user_led'),
sys_clk_freq = sys_clk_freq
)
self.add_csr('leds')

# Buttons
self.submodules.buttons = GPIOIn(
pads = platform.request_all('user_btn')
)
self.add_csr('buttons')

# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
self.cpu.wb_stb,
self.cpu.wb_cyc,
self.cpu.wb_adr,
self.cpu.wb_we,
self.cpu.wb_ack,
self.cpu.wb_sel,
self.cpu.wb_datw,
self.cpu.wb.datr,
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 512,
clock_domain = 'sys',
csr_csv = 'analyzer.csv')
self.add_csr('analyzer')



# Build --------------------------------------------------------------------------------------------

def main():

parser = argparse.ArgumentParser(description='A2O Test')
parser.add_argument('--build', action='store_true', help='Build bitstream')
parser.add_argument('--load', action='store_true', help='Load bitstream')
parser.add_argument('--sys-clk-freq', default=100e6, help='System clock frequency (default: 100MHz)')
parser.add_argument('--with-analyzer', action='store_true', help='Include analyzer')

builder_args(parser)
args = parser.parse_args()

soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_analyzer = args.with_analyzer,
)

builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)

if __name__ == '__main__':
main()

1
build/litex/a2p_new/__init__.py

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from .core import A2P

50
build/litex/a2p_new/boot-helper.S

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.section .text, "ax", @progbits
# called by bios boot commands to do the jump to code (r1,r2,r3 can be specified in terminal 'boot' command)

.include "defines.s"

.global boot_helper
# extern void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr);

.align 4
boot_helper:
lis r3,_fstack@h
ori r3,r3,_fstack@l # top o mem
mtctr r6
bctr # jump to callee

# play with stack. what could go wrong?
# r1 = new top
# orig lr 20(r1)
# ancient r1 16(r1)
# local1 12(r1)
# local2 8(r1)
# (next lr) 4(r1)
# orig r1 0(r1)
# doesnt help...getting a bad op, probably blr to wrong address off stack, within calls to do a putchar
stwu r1,-32(r1)
mflr r0
stw r0,36(r1)
stw r3,8(r1)
stw r4,12(r1)
stw r5,16(r1)
stw r6,20(r1)
li r3,'w'
slwi r3,r3,8
ori r3,r3,'t'
slwi r3,r3,8
ori r3,r3,'f'
slwi r3,r3,8
ori r3,r3,'!'
stw r3,24(r1)
stw r3,28(r1)
lwz r0,36(r1)
mtlr r6
addi r1,r1,32
blr

#addi r1,r1,32 # leave frame on stack
#mtctr r6
#bctrl # jump to callee

b .

150
build/litex/a2p_new/core.py

@ -0,0 +1,150 @@ @@ -0,0 +1,150 @@
#

import os

from migen import *

from litex import get_data_mod
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import *
from litex.soc.cores.cpu import CPU

dir = os.path.dirname(os.path.realpath(__file__))

# these select the top RTL file for each variant name
CPU_VARIANTS = {
'WB': 'A2P',
'standard': 'A2P' #wtf litex does this as default
}

GCC_FLAGS = {
'WB' : '-m32 -mbig-endian -mno-multiple -msoft-float -fno-stack-protector -Xassembler -defsym -Xassembler BIOS_32=1'
}

class A2P(CPU, AutoCSR):
name = 'a2p'
human_name = 'a2p'
variants = CPU_VARIANTS

family = 'powerpc'
data_width = 32
endianness = 'big'
gcc_triple = 'powerpc-linux-gnu'
linker_output_format = 'elf32-powerpc'

nop = 'nop'
io_regions = {0x80000000: 0x80000000} # origin, length

@property
def mem_map(self):
return {
'rom': 0x00000000,
'sram': 0x00004000,
'main_ram': 0x40000000,
'csr': 0xf0000000,
}

@property
def gcc_flags(self):
flags = GCC_FLAGS[self.variant]
flags += ' -D__a2p__'
flags += ' -DCONFIG_BIOS_NO_BOOT=1 -DCONFIG_BIOS_NO_CRC=1 -DCONFIG_MAIN_RAM_INIT=1' #wtf skip crc and ram memtest for now!
return flags

def __init__(self, platform, variant='WB'):

if variant == 'standard':
variant = 'WB'

self.platform = platform
self.variant = variant
self.human_name = 'a2p'
self.external_variant = None
self.reset = Signal()
self.interrupt = Signal(32)
self.interruptS = Signal()
self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface()
self.periph_buses = [ibus, dbus]
self.memory_buses = []
self.enableDebug = False
self.enableJTAG = False
self.externalResetVector = 0

# # #

self.cpu_params = dict(
i_clk = ClockSignal(),
i_reset = ResetSignal() | self.reset,

i_externalInterrupt = self.interrupt[0],
i_externalInterruptS = self.interruptS,
i_timerInterrupt = 0,
i_softwareInterrupt = 0,

#wtf i guess you get these names from the Inteface() def - but what about other sigs?
o_iBusWB_ADR = ibus.adr,
o_iBusWB_DAT_MOSI = ibus.dat_w,
o_iBusWB_SEL = ibus.sel,
o_iBusWB_CYC = ibus.cyc,
o_iBusWB_STB = ibus.stb,
o_iBusWB_WE = ibus.we,
o_iBusWB_CTI = ibus.cti,
o_iBusWB_BTE = ibus.bte,
i_iBusWB_DAT_MISO = ibus.dat_r,
i_iBusWB_ACK = ibus.ack,
i_iBusWB_ERR = ibus.err,

o_dBusWB_ADR = dbus.adr,
o_dBusWB_DAT_MOSI = dbus.dat_w,
o_dBusWB_SEL = dbus.sel,
o_dBusWB_CYC = dbus.cyc,
o_dBusWB_STB = dbus.stb,
o_dBusWB_WE = dbus.we,
o_dBusWB_CTI = dbus.cti,
o_dBusWB_BTE = dbus.bte,
i_dBusWB_DAT_MISO = dbus.dat_r,
i_dBusWB_ACK = dbus.ack,
i_dBusWB_ERR = dbus.err
)

self.cpu_params['i_externalResetVector'] = self.externalResetVector

# these need to connect to top nets
if self.enableDebug:
self.cpu_params['i_debugReset'] = 0
self.cpu_params['o_debug_resetOut'] = 0
self.cpu_params['i_debug_bus_cmd_valid'] = 0
self.cpu_params['i_debug_bus_cmd_ready'] = 0
self.cpu_params['i_debug_bus_cmd_payload_wr'] = 0
self.cpu_params['i_debug_bus_cmd_payload_address'] = 0
self.cpu_params['i_debug_bus_cmd_payload_data'] = 0
self.cpu_params['o_debug_bus_rsp_data'] = 0

if self.enableJTAG:
self.cpu_params['i_jtag_tms'] = 0
self.cpu_params['i_jtag_tck'] = 0
self.cpu_params['i_jtag_tdi'] = 0
self.cpu_params['o_jtag_tdo'] = 0

def set_reset_address(self, reset_address):
assert not hasattr(self, 'reset_address')
self.reset_address = reset_address
self.cpu_params.update(i_externalResetVector=Signal(32, reset=reset_address))

@staticmethod
def add_sources(platform, variant='WB'):
cpu_filename = CPU_VARIANTS[variant] + '.v'
#vdir = get_data_mod('cpu', 'a2p').data_location
vdir = os.path.join(dir, 'verilog')
platform.add_source(os.path.join(vdir, cpu_filename))

def use_external_variant(self, variant_filename):
self.external_variant = True
self.platform.add_source(variant_filename)

def do_finalize(self):
assert hasattr(self, 'reset_address')
if not self.external_variant:
self.add_sources(self.platform, self.variant)
self.specials += Instance('A2P', **self.cpu_params)

261
build/litex/a2p_new/crt0.S

@ -0,0 +1,261 @@ @@ -0,0 +1,261 @@
.include "defines.s"

.set DEBUG,1

.macro load32 rx,v
li \rx,0
oris \rx,\rx,\v>>16
ori \rx,\rx,\v&0x0000FFFF
.endm

.macro load16swiz rx,v
li \rx,0
ori \rx,\rx,(\v<<8)&0xFF00
ori \rx,\rx,(\v>>8)&0x00FF
.endm

.macro delayr rx
mtctr \rx
bdnz .
.endm

.macro delay rx,v
li \rx,0
oris \rx,\rx,\v>>16
ori \rx,\rx,\v&0x0000FFFF
mtctr \rx
bdnz .
.endm

.section .text

.global _start

.org 0x0000

_start:
b boot_start

.set REGSAVE,0x04
regsave:
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0

.org 0x0100
int_100:
b .

# mck
.align 8
int_200:
b .

# dsi
.align 8
int_300:
b .

# dseg
.align 7
int_380:
b .

# isi
.align 8
int_400:
b .

# iseg
.align 7
int_480:
b .

.ifndef DEBUG
# external
.align 8
int_500:
b .

# alignment
.align 8
int_600:
b .

# program
.align 8
int_700:
b .

# fp unavailable
.align 8
int_800:
b .

# dec
.align 8
int_900:
b .

# dec hyp
.align 7
int_980:
b .

# doorbell
.align 8
int_C00:
b .

# trace
.align 8
int_D00:
b .

# dsi hyp
.align 8
int_E00:
b .

# isi hyp
.align 5
int_E20:
b .

# emulation hyp
.align 5
int_E40:
b .

# maintenance hyp
.align 5
int_E60:
b .

# doorbell hyp
.align 5
int_E80:
b .

# virtualization hyp
.align 5
int_EA0:
b .

# reserved
.align 5
int_EC0:
b .

# reserved
.align 5
int_EE0:
b .

# perfmon
.align 5
int_F00:
b .

# vector unavailable
.align 5
int_F20:
b .

# vsx unavailable
.align 5
int_F40:
b .

# facility unavailable
.align 5
int_F60:
b .

# facility unavailable hyp
.align 5
int_F80:
b .

.endif

# ------------------------------------------------------------------------------------------------------------------------------
# init facilities and memories before blastoff
#

.ifdef DEBUG
.org 0x4E4 # match up close to a2o version
.else
.org 0x1000
.endif

boot_start:

rominit:

########################################################################################################################################
# VMA/LMA: copy .data, clear .bss

# get the linker script symbols needed...
lis r1,_fdata_rom@h
ori r1,r1,_fdata_rom@l
lis r2,_fdata@h
ori r2,r2,_fdata@l
lis r3,_edata_rom@h
ori r3,r3,_edata_rom@l
lis r4,_fbss@h
ori r4,r4,_fbss@l
lis r5,_ebss@h
ori r5,r5,_ebss@l

subf r9,r1,r3
srwi. r9,r9,2
beq romcopy_done
mtctr r9
addi r1,r1,-4
addi r2,r2,-4

romcopy:
lwzu r9,4(r1)
stwu r9,4(r2)
bdnz romcopy

romcopy_done:
subf r9,r4,r5
srwi. r9,r9,2
beq romclear_done

mtctr r9
addi r4,r4,-4
li r9,0

romclear:
stwu r9,4(r4)
bdnz romclear

romclear_done:

########################################################################################################################################

########################################################################################################################################

process_start:

jump2main:
lis r1,_fstack@h
ori r1,r1,_fstack@l
addi r1,r1,-16
li r3, 0 # parm 1
b main


.align 4
.ifdef BIOS_32
.include "crtsavres.s"
.endif

129
build/litex/a2p_new/crtsavres.s

@ -0,0 +1,129 @@ @@ -0,0 +1,129 @@
# save/restore for 32b libc

.macro GLOBAL n
.type \n,@function
.global \n
\n:
.endm

# saves

GLOBAL _savegpr_16
stw 16,-64(11)

GLOBAL _savegpr_17
stw 17,-60(11)

GLOBAL _savegpr_18
stw 18,-56(11)

GLOBAL _savegpr_19
stw 19,-52(11)

GLOBAL _savegpr_20
stw 20,-48(11)

GLOBAL _savegpr_21
stw 21,-44(11)

GLOBAL _savegpr_22
stw 22,-40(11)

GLOBAL _savegpr_23
stw 23,-36(11)

GLOBAL _savegpr_24
stw 24,-32(11)

GLOBAL _savegpr_25
stw 25,-28(11)

GLOBAL _savegpr_26
stw 26,-24(11)

GLOBAL _savegpr_27
stw 27,-20(11)

GLOBAL _savegpr_28
stw 28,-16(11)

GLOBAL _savegpr_29
stw 29,-12(11)

GLOBAL _savegpr_30
stw 30,-8(11)

GLOBAL _savegpr_31
stw 31,-4(11)
blr

# restores

GLOBAL _restgpr_16_x
GLOBAL _rest32gpr_16_x
lwz 16,-64(11)

GLOBAL _restgpr_17_x
GLOBAL _rest32gpr_17_x
lwz 17,-60(11)

GLOBAL _restgpr_18_x
GLOBAL _rest32gpr_18_x
lwz 18,-56(11)

GLOBAL _restgpr_19_x
GLOBAL _rest32gpr_19_x
lwz 19,-52(11)

GLOBAL _restgpr_20_x
GLOBAL _rest32gpr_20_x
lwz 20,-48(11)

GLOBAL _restgpr_21_x
GLOBAL _rest32gpr_21_x
lwz 21,-44(11)

GLOBAL _restgpr_22_x
GLOBAL _rest32gpr_22_x
lwz 22,-40(11)

GLOBAL _restgpr_23_x
GLOBAL _rest32gpr_23_x
lwz 23,-36(11)

GLOBAL _restgpr_24_x
GLOBAL _rest32gpr_24_x
lwz 24,-32(11)

GLOBAL _restgpr_25_x
GLOBAL _rest32gpr_25_x
lwz 25,-28(11)

GLOBAL _restgpr_26_x
GLOBAL _rest32gpr_26_x
lwz 26,-24(11)

GLOBAL _restgpr_27_x
GLOBAL _rest32gpr_27_x
lwz 27,-20(11)

GLOBAL _restgpr_28_x
GLOBAL _rest32gpr_28_x
lwz 28,-16(11)

GLOBAL _restgpr_29_x
GLOBAL _rest32gpr_29_x
lwz 29,-12(11)

GLOBAL _restgpr_30_x
GLOBAL _rest32gpr_30_x
lwz 30,-8(11)

GLOBAL _restgpr_31_x
GLOBAL _rest32gpr_31_x
lwz 0,4(11)
lwz 31,-4(11)
mtlr 0
mr 1,11
blr

146
build/litex/a2p_new/defines.s

@ -0,0 +1,146 @@ @@ -0,0 +1,146 @@
# © IBM Corp. 2020
# Licensed under and subject to the terms of the CC-BY 4.0
# license (https://creativecommons.org/licenses/by/4.0/legalcode).
# Additional rights, including the right to physically implement a softcore
# that is compliant with the required sections of the Power ISA
# Specification, will be available at no cost via the OpenPOWER Foundation.
# This README will be updated with additional information when OpenPOWER's
# license is available.

#-----------------------------------------
# Defines
#-----------------------------------------

# Regs

.set r0, 0
.set r1, 1
.set r2, 2
.set r3, 3
.set r4, 4
.set r5, 5
.set r6, 6
.set r7, 7
.set r8, 8
.set r9, 9
.set r10,10
.set r11,11
.set r12,12
.set r13,13
.set r14,14
.set r15,15
.set r16,16
.set r17,17
.set r18,18
.set r19,19
.set r20,20
.set r21,21
.set r22,22
.set r23,23
.set r24,24
.set r25,25
.set r26,26
.set r27,27
.set r28,28
.set r29,29
.set r30,30
.set r31,31

.set f0, 0
.set f1, 1
.set f2, 2
.set f3, 3
.set f4, 4
.set f5, 5
.set f6, 6
.set f7, 7
.set f8, 8
.set f9, 9
.set f10,10
.set f11,11
.set f12,12
.set f13,13
.set f14,14
.set f15,15
.set f16,16
.set f17,17
.set f18,18
.set f19,19
.set f20,20
.set f21,21
.set f22,22
.set f23,23
.set f24,24
.set f25,25
.set f26,26
.set f27,27
.set f28,28
.set f29,29
.set f30,30
.set f31,31

.set cr0, 0
.set cr1, 1
.set cr2, 2
.set cr3, 3
.set cr4, 4
.set cr5, 5
.set cr6, 6
.set cr7, 7

# SPR numbers

.set srr0, 26
.set srr1, 27
.set epcr, 307
.set tar, 815
.set dsisr, 18
.set dar, 19

.set dbsr, 304
.set dbcr0, 308
.set dbcr1, 309
.set dbcr2, 310
.set dbcr3, 848

.set ivpr, 63

.set iucr0, 1011
.set iucr1, 883
.set iucr2, 884

.set iudbg0, 888
.set iudbg1, 889
.set iudbg2, 890
.set iulfsr, 891
.set iullcr, 892

.set mmucr0, 1020
.set mmucr1, 1021
.set mmucr2, 1022
.set mmucr3, 1023

.set tb, 268
.set tbl, 284
.set tbh, 285

.set dec, 22
.set udec, 550
.set tsr, 336
.set tcr, 340

.set xucr0, 1014
.set xucr1, 851
.set xucr2, 1016
.set xucr3, 852
.set xucr4, 853

.set tens, 438
.set tenc, 439
.set tensr, 437

.set pid, 48
.set pir, 286
.set pvr, 287
.set tir, 446

18
build/litex/a2p_new/irq.h

@ -0,0 +1,18 @@ @@ -0,0 +1,18 @@
#ifndef __IRQ_H
#define __IRQ_H

static inline void irq_setmask(unsigned int mask) {
}

static inline unsigned int irq_getmask(void) {
return 0;
}

static inline unsigned int irq_pending(void) {
return 0;
}

static inline void irq_setie(unsigned int mask) {
}

#endif

67
build/litex/a2p_new/system.h

@ -0,0 +1,67 @@ @@ -0,0 +1,67 @@
// a2p
// changed to NOT

#ifndef __SYSTEM_H
#define __SYSTEM_H

#include <stdint.h>

/*
void flush_l2_cache(void) {
}
*/
static void flush_cpu_icache(void);
static void flush_cpu_dcache(void);

static void flush_cpu_icache(void) {
}
static void flush_cpu_dcache(void) {
}


/* CSRs are stored in subregister slices of CONFIG_CSR_DATA_WIDTH (native
* endianness), with the least significant slice at the lowest aligned
* (base) address. */

/* CSR subregisters (a.k.a. "simple CSRs") are embedded inside uint32_t
* aligned locations: */

/*
#define CSR_ACCESSORS_DEFINED


#ifdef __ASSEMBLER__
#define MMPTR(x) x
#else

#include <generated/soc.h>
#if !defined(CONFIG_CSR_DATA_WIDTH)
#error CSR_DATA_WIDTH MUST be set before including this file!
#endif

#define MMPTR(a) (*((volatile uint32_t *)(a)))

static inline unsigned long swizzle(unsigned long v);

static inline unsigned long swizzle(unsigned long v) {
//return ((v & 0x000000FF) << 24) | ((v & 0x0000FF00) << 8) | ((v & 0x00FF0000) >> 8) | ((v & 0xFF000000) >> 24);
return v;
}

static inline void csr_write_simple(unsigned long v, unsigned long a)
{
//MMPTR(a) = v;
MMPTR(a) = swizzle(v);
}

static inline unsigned long csr_read_simple(unsigned long a)
{
//return MMPTR(a);
return swizzle(MMPTR(a));
}

#endif
*/

#endif /* __SYSTEM_H */

14250
build/litex/a2p_new/verilog/A2P_WB.v

File diff suppressed because it is too large Load Diff

27
build/litex/bin2init

@ -0,0 +1,27 @@ @@ -0,0 +1,27 @@
#!/usr/bin/python3

# read .bin (objcopy -O binary x.elf x.bin) and create ascii block file

import sys
from binascii import hexlify, unhexlify

def x2d(i):
return int(i, 16)

inFile = sys.argv[1]
#size = sys.argv[2]

outFile = inFile + '.hex'

lines = []
with open(inFile, 'rb') as binFile:
word = binFile.read(4)
while word:
hex = hexlify(word)
lines.append(hex.decode('utf-8').upper() + '\n')
word = binFile.read(4)

# need to pad to full size?
with open(outFile, 'w') as txtFile:
txtFile.writelines(lines)

14250
sim/soc/A2P_WB.v

File diff suppressed because it is too large Load Diff

17887
sim/soc/bios.s

File diff suppressed because it is too large Load Diff

6199
sim/soc/cmod7_rom.init

File diff suppressed because it is too large Load Diff

52
sim/soc/readme.md

@ -0,0 +1,52 @@ @@ -0,0 +1,52 @@
# Testing full Litex software build

* manually update/install litex picolib for 32BE

* fixes for BE in A2P_4K1W.v

* cp A2P_4K1W.v A2P_WB.v
and edit to rename to module A2P_WB

```
cd ../../build/litex
a2p_a2o_32.py --csr-csv csr.csv
powerpc-linux-gnu-objdump -d build/cmod7/software/bios/bios.elf > bios.d
powerpc-linux-gnu-objdump -s build/cmod7/software/bios/bios.elf > bios.s
bin2init build/cmod7/software/bios/bios.bin

#if rtl updated
#cp a2p/verilog/A2P_WB.v ../../../sim/soc/.
#cp build/cmod7/gateware/cmod.v ../../../sim/soc/soc.v
#sed -i "s/module cmod7/module soc/" soc.v # keep consistent naming for top

cp bios.d ../../../sim/soc/.
cp bios.s ../../../sim/soc/.
cp build/cmod7/software/bios/bios.bin.hex ../../../sim/soc/cmod7_rom.init


cd ../../../sim/soc
top=cmod7
mod=soc
#if rtl updated
#sed -i "s/module $top/module $mod/" $mod.v # keep consistent naming for top

###############################################
# build with or without tracing ###############

dir=obj_dir_${mod}
verilator -cc --exe --CFLAGS -DUART=2593 --trace --Mdir $dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iunisims soc $mod tb_litex_$mod.cpp |& tee verilator_$mod.txt
make -j6 -C $dir -f V$mod.mk V$mod
$dir/V$mod | tee sim_soc.txt

dir=obj_dir_${mod}_notrace
verilator -cc --exe --CFLAGS -DUART=2593 --CFLAGS -DNO_TRACE=1 --Mdir $dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iunisims soc $mod tb_litex_$mod.cpp |& tee verilator_$mod.txt
make -j6 -C $dir -f V$mod.mk V$mod
$dir/V$mod

################################################


vcd2fst a2plitex.vcd soc.fst
rm a2p_soc.vcd
gtkwave soc.fst soc.gtkw
```

1958
sim/soc/soc.v

File diff suppressed because it is too large Load Diff

455
sim/soc/tb_litex_soc.cpp

@ -0,0 +1,455 @@ @@ -0,0 +1,455 @@
// simple verilator top
// litex soc w/a2p

#ifndef NO_TRACE
#define TRACING
#endif

// old public access method
//#define OLD_PUBLIC

#include <cstddef>
#include <iostream>
#include <fstream>
#include <iomanip>
#include <unordered_map>

#include "verilated.h"
#include "Vsoc.h"

#ifndef OLD_PUBLIC
// internal nets
#include "Vsoc___024root.h"
#endif

#include "Vsoc_soc.h"
#include "Vsoc_A2P_WB.h"

#ifdef TRACING
#include "verilated_vcd_c.h"
VerilatedVcdC *t;
#else
unsigned int t = 0;
#endif

// using https://github.com/ZipCPU/wbuart32 sim driver
// how does cpp get compiled in without this? can verilator be told to add more cpp? see a2p!
// UART=port
// 0xA20 = 2592
// A2P = 2593
#ifdef UART
#include "wbuart32/bench/cpp/uartsim.h"
#include "wbuart32/bench/cpp/uartsim.cpp"
#endif

Vsoc* m;
#ifdef OLD_PUBLIC
Vsoc* root;
#else
Vsoc___024root* root;
#endif

vluint64_t main_time = 0; // in units of timeprecision used in verilog or --timescale-override

double sc_time_stamp() { // $time in verilog
return main_time;
}

const char* tbName = "tb_litex_soc";
const int resetCycle = 10;
const int threadRunCycle = resetCycle + 5;
const int runCycles = 1000000000;
const int hbCycles = 500;
const int quiesceCycles = 50;
const int threads = 1;
const std::string testFile = "";
const unsigned int bootAdr = 0x00000000;
const bool failMaxCycles = true;
const unsigned int stopOnHang = 500;
const unsigned int stopOnLoop = 20;
const unsigned long iarPass = 0x7F0;
const unsigned long iarFail = 0x7F4;
const bool debugWB = true;
const bool debugWBReq = false;

// Cythonize this and use it for cocotb too...

class Memory {
std::unordered_map<unsigned int, unsigned int> mem;
public:
bool le;
bool logStores;
int defaultVal;
Memory();
void loadFile(std::string filename, unsigned int adr=0, bool le=false, std::string format="ascii");
int read(unsigned int adr);
void write(unsigned int adr, unsigned int dat);
void write(unsigned int adr, unsigned int be, unsigned int dat);
};

Memory::Memory() {

this->defaultVal = 0;
this->le = false;
this->logStores = true;

}

void Memory::loadFile(std::string filename, unsigned int adr, bool le, std::string format) {

unsigned int dat;
std::ifstream f;
f.open(filename, std::fstream::in);
// "ascii"
//while (f.peek()!=EOF) {
//f >> std::hex >> dat;
// f >> dat;
while (f >> std::hex >> dat) {
this->write(adr, dat);
adr += 4;
}

}

// adr is word-aligned byte address
int Memory::read(unsigned int adr) {
if (this->mem.find(adr) != this->mem.end()) {
return this->mem[adr];
} else {
return this->defaultVal;
}
}

// adr is word-aligned byte address
void Memory::write(unsigned int adr, unsigned int dat) {
unsigned int startDat = this->read(adr);
this->write(adr, 0xF, dat);
}

void Memory::write(unsigned int adr, unsigned int be, unsigned int dat) {
if (be == 0) return;

int mask = 0, startDat;
if (be >= 8) {
be = be - 8;
mask = 0xFF000000;
} else {
mask = 0;
}
if (be >= 4) {
be = be - 4;
mask |= 0x00FF0000;
}
if (be >= 2) {
be = be - 2;
mask |= 0x0000FF00;
}
if (be = 1) {
mask |= 0x000000FF;
}

startDat = this->read(adr);
this->mem[adr] = (startDat & ~mask) | (dat & mask);
if (this->logStores) {
std::cout << " * Mem Update @" << std::setw(8) << std::setfill('0') << std::uppercase << std::hex << adr <<
" " <<std::setw(8) << std::setfill('0') << std::uppercase << std::hex << startDat <<
"->" <<std::setw(8) << std::setfill('0') << std::uppercase << std::hex << this->read(adr) << std::endl;
}
}

Memory mem;

int main(int argc, char **argv) {
using namespace std;

cout << setfill('0');

Verilated::commandArgs(argc, argv);
m = new Vsoc;
#ifdef OLD_PUBLIC
root = m;
#else
root = m->rootp;
#endif

#ifdef TRACING
Verilated::traceEverOn(true);
t = new VerilatedVcdC;
m->trace(t, 99);
t->open("a2plitex.vcd");
cout << "Tracing enabled." << endl;
#endif

unsigned int i, v;
bool ok = true;
bool done = false;
bool resetDone = false;
bool booted = false;
unsigned int quiesceCount = 0;
unsigned int threadStop = 0x3;

unsigned int tick = 0;
unsigned int cycle = 1;
unsigned int readPending = 0;
unsigned int readAddr = 0;
unsigned int readTag = 0;
unsigned int readTID = 0;
unsigned int countReads = 0;
unsigned int lastCompCycle = 0;
unsigned int lastCompSame = 0;
unsigned int lastCompIAR = 0x0000001;
unsigned int gpr[32];
bool wbRdPending = false, wbWrPending = false;

// memory setup
//mem.write(0xFFFFFFFC, 0x48000002);
//mem.loadFile(testFile);

// uart setup
/*
// i_setup[30] True if we are not using hardware flow control. This bit
// is ignored within this module, as any receive hardware flow
// control will need to be implemented elsewhere.
//
// i_setup[29:28] Indicates the number of data bits per word. This will
// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
// for a six bit word, or 2'b11 for a five bit word.
//
// i_setup[27] Indicates whether or not to use one or two stop bits.
// Set this to one to expect two stop bits, zero for one.
//
// i_setup[26] Indicates whether or not a parity bit exists. Set this
// to 1'b1 to include parity.
//
// i_setup[25] Indicates whether or not the parity bit is fixed. Set
// to 1'b1 to include a fixed bit of parity, 1'b0 to allow the
// parity to be set based upon data. (Both assume the parity
// enable value is set.)
//
// i_setup[24] This bit is ignored if parity is not used. Otherwise,
// in the case of a fixed parity bit, this bit indicates whether
// mark (1'b1) or space (1'b0) parity is used. Likewise if the
// parity is not fixed, a 1'b1 selects even parity, and 1'b0
// selects odd.
//
// i_setup[23:0] Indicates the speed of the UART in terms of clocks.
// So, for example, if you have a 200 MHz clock and wish to
// run your UART at 9600 baud, you would take 200 MHz and divide
// by 9600 to set this value to 24'd20834. Likewise if you wished
// to run this serial port at 115200 baud from a 200 MHz clock,
// you would set the value to 24'd1736
*/
/*
m_baud_counts = (isetup & 0x0ffffff);
m_nbits = 8-((isetup >> 28)&0x03);
m_nstop =((isetup >> 27)&1)+1;
m_nparity = (isetup >> 26)&1;
m_fixdp = (isetup >> 25)&1;
m_evenp = (isetup >> 24)&1;
*/

// 100MHz, 115200 = 868
#ifdef UART
UARTSIM *uart;
int uartPort = UART; // 0-stdin/stdout
//unsigned uartConfig = 1736;
unsigned uartConfig = 868;
//unsigned uartConfig = 434;
//unsigned uartConfig = 217;
//unsigned uartConfig = 217;

cout << "Initializing UART on port " << uartPort << " with config=" << hex << setw(8) << setfill('0') << uartConfig << endl;
uart = new UARTSIM(uartPort);
uart->setup(uartConfig);
cout << "litex_term socket://localhost:" << uartPort << " in a console, then hit enter here...." << endl;
cin.get();
#endif


// do something

for (i = 0; i < 32; i++) {
gpr[i] = 0;
}

//just use hardware reset
//root->soc->main_basesoc_soc_rst = 1;
//cout << dec << setw(8) << cycle << " Resetting..." << endl;

const int clocks[2] = {0x1, 0x0}; // 1x
const int ticks1x = 2;

while (!Verilated::gotFinish() && (ok | quiesceCount > 0) && cycle <= runCycles && !done) {

if (!resetDone && (cycle > resetCycle)) {
//root->soc->main_basesoc_soc_rst = 0;
//cout << dec << setw(8) << cycle << " Releasing reset." << endl;
resetDone = true;
}

if (threadStop && (cycle > threadRunCycle)) {
//threadStop = 0x0;
//m->an_ac_pm_thread_stop = threadStop;
//cout << dec << setw(8) << cycle << " Thread stop=" << threadStop << endl;
}

m->clk12 = clocks[tick % ticks1x];
m->eval();

// 1x clock
if ((tick % ticks1x) == 0) {

// core

// completion
if (root->soc->A2P_WB->lastStageIsFiring) {
v = root->soc->A2P_WB->lastStagePc;
cout << dec << setw(8) << setfill('0') << uppercase << cycle << " C0: CP";
cout << " 0:" << setw(6) << setfill('0') << hex << v;
cout << " [" << setw(6) << setfill('0') << hex << root->soc->A2P_WB->lastStageInstruction << "]" << endl;
if (quiesceCount > 0) {
/* skip remaining checks */
} else if (v == iarPass) {
cout << "*** Passing IAR detected ***" << endl;
quiesceCount = 5;
} else if (v == iarFail) {
cout << "*** Failing IAR detected ***" << endl;
ok = false;
quiesceCount = 5;
} else if (v == lastCompIAR) {
lastCompSame++;
if (stopOnLoop && (lastCompSame == stopOnLoop)) {
ok = false;
cout << "*** Loop detected for " << dec << stopOnLoop << " iterations ***" << endl;
}
} else {
lastCompIAR = v;
lastCompSame = 0;
}
}

// gpr change - really need to use these (to detect write w/same data)
//reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
//reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
//wire UpdateRegFileWrite_valid /* verilator public */ ;
//wire UpdateRegFileWrite_payload_valid /* verilator public */ ;
//wire [4:0] UpdateRegFileWrite_payload_address /* verilator public */ ;
//wire [31:0] UpdateRegFileWrite_payload_data /* verilator public */ ;

for (i = 0; i < 32; i++) {
v = root->soc->A2P_WB->RegFilePlugin_regFile[i];
if (v != gpr[i]) {
gpr[i] = v;
cout << dec << setw(8) << setfill('0') << cycle << " C0: GPR Update: R";
cout << dec << setw(2) << setfill('0') << i << "=";
cout << hex << setw(8) << setfill('0') << uppercase << v << " ";
cout << endl;
}
}


// completion

// wb - soc can monitor-only
if (wbRdPending) {
if (root->soc->A2P_WB->dBusWB_ACK)
if (debugWB)
cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB RD ACK RA=" << setw(8) << hex << setfill('0') << (root->soc->A2P_WB->dBusWB_ADR << 2) <<
" DATA=" << setw(8) << hex << setfill('0') << root->soc->A2P_WB->dBusWB_DAT_MISO << endl;

wbRdPending = false;

} else if (wbWrPending) {
if (root->soc->A2P_WB->dBusWB_ACK)
if (debugWB)
cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB WR ACK RA=" << setw(8) << hex << setfill('0') << (root->soc->A2P_WB->dBusWB_ADR << 2) <<
" SEL=" << setw(1) << setfill('0') << uppercase << hex << (unsigned int)root->soc->A2P_WB->dBusWB_SEL <<
" DATA=" << setw(8) << hex << setfill('0') << root->soc->A2P_WB->dBusWB_DAT_MOSI << endl;
wbWrPending = false;

} else if (root->soc->A2P_WB->dBusWB_CYC && root->soc->A2P_WB->dBusWB_STB) {
if (!root->soc->A2P_WB->dBusWB_WE) {
if (root->soc->A2P_WB->dBusWB_ACK) {
if (debugWB)
cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB RD ACK RA=" << setw(8) << hex << setfill('0') << (root->soc->A2P_WB->dBusWB_ADR << 2) <<
" DATA=" << setw(8) << hex << setfill('0') << root->soc->A2P_WB->dBusWB_DAT_MISO << endl;
} else if (!wbRdPending && debugWBReq) {
cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB RD RA=" << setw(8) << hex << setfill('0') << (root->soc->A2P_WB->dBusWB_ADR << 2) << endl;
wbRdPending = true;
}
} else {
if (debugWB) {
cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB WR ACK RA=" << setw(8) << hex << setfill('0') << (root->soc->A2P_WB->dBusWB_ADR << 2) <<
" SEL=" << setw(1) << setfill('0') << uppercase << hex << (unsigned int)root->soc->A2P_WB->dBusWB_SEL <<
" DATA=" << setw(8) << hex << setfill('0') << root->soc->A2P_WB->dBusWB_DAT_MOSI << endl;
} else if (!wbWrPending && debugWBReq) {
cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB WR RA=" << setw(8) << hex << setfill('0') << (root->soc->A2P_WB->dBusWB_ADR << 2) <<
" SEL=" << root->soc->A2P_WB->dBusWB_SEL << " DATA=" << setw(8) << hex << setfill('0') << root->soc->A2P_WB->dBusWB_DAT_MOSI << endl;
wbWrPending = true;
}
}
}

// leds, btns, mem, etc.

} else {

if (resetDone) {
#ifdef UART
m->serial_rx = (*uart)(m->serial_tx);
#endif
}

}

m->eval(); // NEED THIS!!!!

// finish clock stuff
if ((tick % ticks1x) == 0) {
cycle++;
if ((cycle % hbCycles) == 0) {
cout << dec << setw(8) << setfill('0') << cycle << " ...tick..." << endl;
}
if (failMaxCycles && (cycle == runCycles)) {
cout << "*** Max cycles reached ***" << endl;
ok = false;
}
}

tick++;

#ifdef TRACING
t->dump(tick);
t->flush();
#endif

// check for fails

if (!ok && quiesceCount == 0) {
quiesceCount = quiesceCycles;
cout << "Quiescing..." << endl;
} else if (quiesceCount > 0) {
quiesceCount--;
if (ok && quiesceCount == 0) {
done = true;
}
}

}

#ifdef TRACING
t->close();
#endif
m->final();

cout << endl << endl << tbName << endl;
cout << endl << "Cycles run=" << dec << cycle << endl << endl;
if (!ok) {
cout << "You are worthless and weak." << endl;
exit(EXIT_FAILURE);
} else {
cout << "You has opulence." << endl;
exit(EXIT_SUCCESS);
}

}

4
sim/soc/unisims/BUFG.v

@ -0,0 +1,4 @@ @@ -0,0 +1,4 @@
module BUFG (output O, input I);
assign O = I;
endmodule

10
sim/soc/unisims/DNA_PORT.v

@ -0,0 +1,10 @@ @@ -0,0 +1,10 @@
module DNA_PORT (DOUT, CLK, DIN, READ, SHIFT);

parameter [56:0] SIM_DNA_VALUE = 57'h0;

output DOUT;
input CLK, DIN, READ, SHIFT;

assign DOUT = 1'b0;

endmodule

21
sim/soc/unisims/FD.v

@ -0,0 +1,21 @@ @@ -0,0 +1,21 @@

`timescale 1 ps / 1 ps

module FD (Q, C, D);

parameter INIT = 1'b0;

output Q;
input C, D;

wire Q;
reg q_out;

initial q_out = INIT;

always @(posedge C)
q_out <= D;

assign Q = q_out;

endmodule

24
sim/soc/unisims/FDCE.v

@ -0,0 +1,24 @@ @@ -0,0 +1,24 @@
`timescale 1 ps / 1 ps

module FDCE (C, CE, CLR, D, Q);

parameter INIT = 1'b1;

output Q;

input C, CE, D, CLR;

wire Q;
reg q_out;

initial q_out = INIT;

assign Q = q_out;

always @(posedge C or posedge CLR)
if (CLR)
q_out <= 0;
else if (CE)
q_out <= D;

endmodule

24
sim/soc/unisims/FDPE.v

@ -0,0 +1,24 @@ @@ -0,0 +1,24 @@
`timescale 1 ps / 1 ps

module FDPE (Q, C, CE, D, PRE);

parameter INIT = 1'b1;

output Q;

input C, CE, D, PRE;

wire Q;
reg q_out;

initial q_out = INIT;

assign Q = q_out;

always @(posedge C or posedge PRE)
if (PRE)
q_out <= 1;
else if (CE)
q_out <= D;

endmodule

10
sim/soc/unisims/IDELAYCTRL.v

@ -0,0 +1,10 @@ @@ -0,0 +1,10 @@
module IDELAYCTRL #(
)(
output RDY,
input REFCLK,
input RST
);

assign RDY = !RST;
endmodule

24
sim/soc/unisims/IDELAYE2.v

@ -0,0 +1,24 @@ @@ -0,0 +1,24 @@
// wtf didn't check what it actually does!

module IDELAYE2 #(
parameter CINVCTRL_SEL,
parameter DELAY_SRC,
parameter HIGH_PERFORMANCE_MODE,
parameter IDELAY_TYPE,
parameter IDELAY_VALUE,
parameter PIPE_SEL,
parameter REFCLK_FREQUENCY,
parameter SIGNAL_PATTERN
)(
input C,
input CE,
input IDATAIN,
input INC,
input LD,
input LDPIPEEN,
output DATAOUT
);

assign DATAOUT = IDATAIN;
endmodule

13
sim/soc/unisims/IOBUF.v

@ -0,0 +1,13 @@ @@ -0,0 +1,13 @@
//wtf nop

module IOBUF #(
)
(
input I,
input T,
inout IO,
inout O
);

endmodule

13
sim/soc/unisims/IOBUFDS.v

@ -0,0 +1,13 @@ @@ -0,0 +1,13 @@
//wtf nop

module IOBUFDS #(
)
(
input I,
input T,
inout IO,
inout IOB
);

endmodule

31
sim/soc/unisims/ISERDESE2.v

@ -0,0 +1,31 @@ @@ -0,0 +1,31 @@
//wtf doesnt do nothin!

module ISERDESE2 #(
parameter DATA_RATE,
parameter DATA_WIDTH,
parameter INTERFACE_TYPE,
parameter IOBDELAY,
parameter NUM_CE,
parameter SERDES_MODE
)
(
input BITSLIP,
input CE1,
input CLK,
input CLKB,
input CLKDIV,
input DDLY,
input RST,
output Q1,
output Q2,
output Q3,
output Q4,
output Q5,
output Q6,