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all dffram

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master
wtf 3 years ago
parent 5758606175
commit 6971fe4b5d
120 changed files with 724278 additions and 28 deletions
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467
build/openroad/Makefile-STA
Unescape Escape View File

@ -0,0 +1,467 @@
# wtf partial make for synth/timing only

export SCRIPTS_DIR = ./scripts

SYNTH_SCRIPT ?= $(SCRIPTS_DIR)/synth.tcl

FLOORPLAN_SCRIPT ?= $(SCRIPTS_DIR)/floorplan.tcl
IO_PLACE_RANDOM_SCRIPT ?= $(SCRIPTS_DIR)/io_placement_random.tcl
TDMS_SCRIPT ?= $(SCRIPTS_DIR)/tdms_place.tcl
MACRO_PLACE_SCRIPT ?= $(SCRIPTS_DIR)/macro_place.tcl

IO_PLACE_SCRIPT ?= $(SCRIPTS_DIR)/io_placement.tcl
GLOBAL_PLACE_SCRIPT ?= $(SCRIPTS_DIR)/global_place.tcl
RESIZE_SCRIPT ?= $(SCRIPTS_DIR)/resize.tcl

RUN_ALL_SCRIPT ?= $(SCRIPTS_DIR)/run_all.tcl
FINAL_REPORT_SCRIPT ?= $(SCRIPTS_DIR)/final_report.tcl


# # Global override Floorplan
# export CORE_UTILIZATION := 30
# export CORE_ASPECT_RATIO := 1
# export CORE_MARGIN := 4

default: finish

# ==============================================================================
# ____ _____ _____ _ _ ____
# / ___|| ____|_ _| | | | _ \
# \___ \| _| | | | | | | |_) |
# ___) | |___ | | | |_| | __/
# |____/|_____| |_| \___/|_|
#
# ==============================================================================

# Include design and platform configuration
include $(DESIGN_CONFIG)

PUBLIC=nangate45 sky130hd sky130hs asap7

ifneq ($(wildcard $(PLATFORM_BASE)/$(PLATFORM)),)
export PLATFORM_DIR = $(PLATFORM_BASE)/$(PLATFORM)
else ifneq ($(findstring $(PLATFORM),$(PUBLIC)),)
export PLATFORM_DIR = ./platforms/$(PLATFORM)
else ifneq ($(wildcard ../../$(PLATFORM)),)
export PLATFORM_DIR = ../../$(PLATFORM)
else
$(error [ERROR][FLOW] Platform '$(PLATFORM)' not found)
endif

$(info [INFO][FLOW] Using platform directory $(PLATFORM_DIR))
include $(PLATFORM_DIR)/config.mk

export FLOW_VARIANT ?= base

# Setup working directories
export DESIGN_NICKNAME ?= $(DESIGN_NAME)

export LOG_DIR = ./logs/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)
export OBJECTS_DIR = ./objects/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)
export REPORTS_DIR = ./reports/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)
export RESULTS_DIR = ./results/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)

export UTILS_DIR = ./util
export TEST_DIR = ./test

# Tool Options
SHELL = /bin/bash -o pipefail

TIME_CMD = /usr/bin/time -f "%Eelapsed %PCPU %MmemKB"
TIME_TEST = $(shell $(TIME_CMD) echo foo 2>/dev/null)
ifeq (, $(strip $(TIME_TEST)))
TIME_CMD = /usr/bin/time
endif

ifeq (, $(strip $(NPROC)))
# Linux (utility program)
NPROC := $(shell nproc 2>/dev/null)

ifeq (, $(strip $(NPROC)))
# Linux (generic)
NPROC := $(shell grep -c ^processor /proc/cpuinfo 2>/dev/null)
endif
ifeq (, $(strip $(NPROC)))
# BSD (at least FreeBSD and Mac OSX)
NPROC := $(shell sysctl -n hw.ncpu 2>/dev/null)
endif
ifeq (, $(strip $(NPROC)))
# Fallback
NPROC := 1
endif
endif
export NUM_CORES := $(NPROC)

OPENROAD_CMD = openroad -no_init -exit
OPENROAD_NO_EXIT_CMD = $(patsubst -exit,,$(OPENROAD_CMD))

WRAPPED_LEFS = $(foreach lef,$(notdir $(WRAP_LEFS)),$(OBJECTS_DIR)/lef/$(lef:.lef=_mod.lef))
WRAPPED_LIBS = $(foreach lib,$(notdir $(WRAP_LIBS)),$(OBJECTS_DIR)/$(lib:.lib=_mod.lib))
export ADDITIONAL_LEFS += $(WRAPPED_LEFS) $(WRAP_LEFS)
export LIB_FILES += $(WRAP_LIBS) $(WRAPPED_LIBS)

export DONT_USE_LIBS = $(addprefix $(OBJECTS_DIR)/lib/, $(notdir $(LIB_FILES)))
export DONT_USE_SC_LIB ?= $(OBJECTS_DIR)/lib/$(notdir $(firstword $(LIB_FILES)))

# Stream system used for final result (GDS is default): GDS, GSDII, GDS2, OASIS, or OAS
STREAM_SYSTEM ?= GDS
ifneq ($(findstring GDS,$(shell echo $(STREAM_SYSTEM) | tr '[:lower:]' '[:upper:]')),)
export STREAM_SYSTEM_EXT := gds
GDSOAS_FILES = $(GDS_FILES)
ADDITIONAL_GDSOAS = $(ADDITIONAL_GDS)
SEAL_GDSOAS = $(SEAL_GDS)
else
export STREAM_SYSTEM_EXT := oas
GDSOAS_FILES = $(OAS_FILES)
ADDITIONAL_GDSOAS = $(ADDITIONAL_OAS)
SEAL_GDSOAS = $(SEAL_OAS)
endif
export WRAPPED_GDSOAS = $(foreach lef,$(notdir $(WRAP_LEFS)),$(OBJECTS_DIR)/$(lef:.lef=_mod.$(STREAM_SYSTEM_EXT)))

# Utility to print tool version information
#-------------------------------------------------------------------------------
.PHONY: versions.txt
versions.txt:
@yosys -V > $@
@echo openroad `$(firstword $(OPENROAD_CMD)) -version` >> $@
@klayout -zz -v >> $@

# Pre-process libraries
# ==============================================================================

# Create temporary Liberty files which have the proper dont_use properties set
# For use with Yosys and ABC
.SECONDEXPANSION:
$(DONT_USE_LIBS): $$(filter %$$(@F),$(LIB_FILES))
@mkdir -p $(OBJECTS_DIR)/lib
$(UTILS_DIR)/markDontUse.py -p "$(DONT_USE_CELLS)" -i $^ -o $@

$(OBJECTS_DIR)/lib/merged.lib:
$(UTILS_DIR)/mergeLib.pl $(PLATFORM)_merged $(DONT_USE_LIBS) > $@

# Pre-process KLayout tech
# ==============================================================================
#$(OBJECTS_DIR)/klayout_tech.lef: $(TECH_LEF)
# @mkdir -p $(OBJECTS_DIR)
# sed '/OR_DEFAULT/d' $< > $@

# $(OBJECTS_DIR)/klayout.lyt: $(KLAYOUT_TECH_FILE) $(OBJECTS_DIR)/klayout_tech.lef
# sed 's,<lef-files>.*</lef-files>,$(foreach file, $(OBJECTS_DIR)/klayout_tech.lef $(SC_LEF) $(ADDITIONAL_LEFS),<lef-files>$(abspath $(file))</lef-files>),g' $< > $@

#$(OBJECTS_DIR)/klayout_wrap.lyt: $(KLAYOUT_TECH_FILE) $(OBJECTS_DIR)/klayout_tech.lef
# sed 's,<lef-files>.*</lef-files>,$(foreach file, $(OBJECTS_DIR)/klayout_tech.lef $(WRAP_LEFS),<lef-files>$(abspath $(file))</lef-files>),g' $< > $@
# Create Macro wrappers (if necessary)
# ==============================================================================
#WRAP_CFG = $(PLATFORM_DIR)/wrapper.cfg

export TCLLIBPATH := util/cell-veneer $(TCLLIBPATH)
$(WRAPPED_LEFS):
mkdir -p $(OBJECTS_DIR)/lef $(OBJECTS_DIR)/def
util/cell-veneer/wrap.tcl -cfg $(WRAP_CFG) -macro $(filter %$(notdir $(@:_mod.lef=.lef)),$(WRAP_LEFS))
mv $(notdir $@) $@
mv $(notdir $(@:lef=def)) $(dir $@)../def/$(notdir $(@:lef=def))

$(WRAPPED_LIBS):
mkdir -p $(OBJECTS_DIR)/lib
sed 's/library(\(.*\))/library(\1_mod)/g' $(filter %$(notdir $(@:_mod.lib=.lib)),$(WRAP_LIBS)) | sed 's/cell(\(.*\))/cell(\1_mod)/g' > $@

# ==============================================================================
# ______ ___ _ _____ _ _ _____ ____ ___ ____
# / ___\ \ / / \ | |_ _| | | | ____/ ___|_ _/ ___|
# \___ \\ V /| \| | | | | |_| | _| \___ \| |\___ \
# ___) || | | |\ | | | | _ | |___ ___) | | ___) |
# |____/ |_| |_| \_| |_| |_| |_|_____|____/___|____/
#
synth: versions.txt \
$(RESULTS_DIR)/1_synth.v \
$(RESULTS_DIR)/1_synth.sdc
# ==============================================================================


# Run Synthesis using yosys
#-------------------------------------------------------------------------------

$(RESULTS_DIR)/1_1_yosys.v: $(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DONT_USE_SC_LIB) $(VERILOG_FILES)
mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR)
($(TIME_CMD) yosys -c $(SYNTH_SCRIPT)) 2>&1 | tee $(LOG_DIR)/1_1_yosys.log

$(RESULTS_DIR)/1_synth.v: $(RESULTS_DIR)/1_1_yosys.v
mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR)
cp $< $@

$(RESULTS_DIR)/1_synth.sdc: $(SDC_FILE)
mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR)
cp $< $@

clean_synth:
rm -f $(RESULTS_DIR)/1_*.v $(RESULTS_DIR)/1_synth.sdc
rm -f $(REPORTS_DIR)/synth_*
rm -f $(LOG_DIR)/1_*
rm -rf _tmp_yosys-abc-*


# ==============================================================================
# _____ _ ___ ___ ____ ____ _ _ _ _
# | ___| | / _ \ / _ \| _ \| _ \| | / \ | \ | |
# | |_ | | | | | | | | | |_) | |_) | | / _ \ | \| |
# | _| | |__| |_| | |_| | _ <| __/| |___ / ___ \| |\ |
# |_| |_____\___/ \___/|_| \_\_| |_____/_/ \_\_| \_|
#
floorplan: $(RESULTS_DIR)/2_floorplan.def \
$(RESULTS_DIR)/2_floorplan.sdc
# ==============================================================================


# STEP 1: Translate verilog to def
#-------------------------------------------------------------------------------
$(RESULTS_DIR)/2_1_floorplan.def: $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(FOOTPRINT) $(SIG_MAP_FILE)
($(TIME_CMD) $(OPENROAD_CMD) $(FLOORPLAN_SCRIPT) -metrics $(LOG_DIR)/2_1_floorplan.json) 2>&1 | tee $(LOG_DIR)/2_1_floorplan.log


# STEP 2: IO Placement
#-------------------------------------------------------------------------------
$(RESULTS_DIR)/2_2_floorplan_io.def: $(RESULTS_DIR)/2_1_floorplan.def $(IO_CONSTRAINTS)
($(TIME_CMD) $(OPENROAD_CMD) $(IO_PLACE_RANDOM_SCRIPT) -metrics $(LOG_DIR)/2_2_floorplan_io.json) 2>&1 | tee $(LOG_DIR)/2_2_floorplan_io.log

# STEP 3: Timing Driven Mixed Sized Placement
#-------------------------------------------------------------------------------
$(RESULTS_DIR)/2_3_floorplan_tdms.def: $(RESULTS_DIR)/2_2_floorplan_io.def $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(LIB_FILES)
($(TIME_CMD) $(OPENROAD_CMD) $(TDMS_SCRIPT) -metrics $(LOG_DIR)/2_3_tdms.json) 2>&1 | tee $(LOG_DIR)/2_3_tdms_place.log

# STEP 4: Macro Placement
#-------------------------------------------------------------------------------
$(RESULTS_DIR)/2_4_floorplan_macro.def: $(RESULTS_DIR)/2_3_floorplan_tdms.def $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(MACRO_PLACEMENT)
($(TIME_CMD) $(OPENROAD_CMD) $(MACRO_PLACE_SCRIPT) -metrics $(LOG_DIR)/2_4_mplace.json) 2>&1 | tee $(LOG_DIR)/2_4_mplace.log

# STEP 5: Tapcell and Welltie insertion
#-------------------------------------------------------------------------------
#$(RESULTS_DIR)/2_5_floorplan_tapcell.def: $(RESULTS_DIR)/2_4_floorplan_macro.def $(TAPCELL_TCL)
# ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/tapcell.tcl -metrics $(LOG_DIR)/2_5_tapcell.json) 2>&1 | tee $(LOG_DIR)/2_5_tapcell.log

# STEP 6: PDN generation
#-------------------------------------------------------------------------------
#$(RESULTS_DIR)/2_6_floorplan_pdn.def: $(RESULTS_DIR)/2_5_floorplan_tapcell.def $(PDN_CFG)
# ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/pdn.tcl -metrics $(LOG_DIR)/2_6_pdn.json) 2>&1 | tee $(LOG_DIR)/2_6_pdn.log

#$(RESULTS_DIR)/2_floorplan.def: $(RESULTS_DIR)/2_6_floorplan_pdn.def
# cp $< $@

#$(RESULTS_DIR)/2_floorplan.sdc: $(RESULTS_DIR)/2_1_floorplan.def

#$(RESULTS_DIR)/2_floorplan.def: $(RESULTS_DIR)/2_3_floorplan_tdms.def
# cp $< $@
$(RESULTS_DIR)/2_floorplan.def: $(RESULTS_DIR)/2_4_floorplan_macro.def
cp $< $@

$(RESULTS_DIR)/2_floorplan.sdc: $(RESULTS_DIR)/2_1_floorplan.def

clean_floorplan:
rm -f $(RESULTS_DIR)/2_*floorplan*.def $(RESULTS_DIR)/2_floorplan.sdc $(RESULTS_DIR)/2_floorplan.v
rm -f $(REPORTS_DIR)/2_*
rm -f $(LOG_DIR)/2_*

# ==============================================================================
# ____ _ _ ____ _____
# | _ \| | / \ / ___| ____|
# | |_) | | / _ \| | | _|
# | __/| |___ / ___ \ |___| |___
# |_| |_____/_/ \_\____|_____|
#
place: $(RESULTS_DIR)/3_place.def \
$(RESULTS_DIR)/3_place.sdc
# ==============================================================================

#wtf this only runs if there are macros
# STEP 1: Global placement + IO placement (not random)
#-------------------------------------------------------------------------------
$(RESULTS_DIR)/3_1_place_gp.def: $(RESULTS_DIR)/2_floorplan.def $(RESULTS_DIR)/2_floorplan.sdc $(LIB_FILES)
($(TIME_CMD) $(OPENROAD_CMD) $(GLOBAL_PLACE_SCRIPT) -metrics $(LOG_DIR)/3_1_place_gp.json) 2>&1 | tee $(LOG_DIR)/3_1_place_gp.log

# STEP 2: IO placement (non-random)
#-------------------------------------------------------------------------------
$(RESULTS_DIR)/3_2_place_iop.def: $(RESULTS_DIR)/3_1_place_gp.def $(IO_CONSTRAINTS)
($(TIME_CMD) $(OPENROAD_CMD) $(IO_PLACE_SCRIPT) -metrics $(LOG_DIR)/3_2_place_iop.json) 2>&1 | tee $(LOG_DIR)/3_2_place_iop.log

# STEP 3: Resizing & Buffering
#-------------------------------------------------------------------------------
#wtf use above steps
#$(RESULTS_DIR)/3_3_place_resized.def: $(RESULTS_DIR)/3_2_place_iop.def $(RESULTS_DIR)/2_floorplan.sdc
# ($(TIME_CMD) $(OPENROAD_CMD) $(RESIZE_SCRIPT) -metrics $(LOG_DIR)/3_3_resizer.json) 2>&1 | tee $(LOG_DIR)/3_3_resizer.log
#wtf just use fp
$(RESULTS_DIR)/3_3_place_resized.def: $(RESULTS_DIR)/2_floorplan.def $(RESULTS_DIR)/2_floorplan.sdc
($(TIME_CMD) $(OPENROAD_CMD) $(RESIZE_SCRIPT) -metrics $(LOG_DIR)/3_3_resizer.json) 2>&1 | tee $(LOG_DIR)/3_3_resizer.log


clean_resize:
rm -f $(RESULTS_DIR)/3_3_place_resized.def

# STEP 4: Detail placement
#-------------------------------------------------------------------------------
#$(RESULTS_DIR)/3_4_place_dp.def: $(RESULTS_DIR)/3_3_place_resized.def
# ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/detail_place.tcl -metrics $(LOG_DIR)/3_4_opendp.json) 2>&1 | tee $(LOG_DIR)/3_4_opendp.log

$(RESULTS_DIR)/3_place.def: $(RESULTS_DIR)/3_3_place_resized.def
cp $< $@

$(RESULTS_DIR)/3_place.sdc: $(RESULTS_DIR)/2_floorplan.sdc
cp $< $@

# Clean Targets
#-------------------------------------------------------------------------------
clean_place:
rm -f $(RESULTS_DIR)/3_*place*.def
rm -f $(RESULTS_DIR)/3_place.sdc
rm -f $(REPORTS_DIR)/3_*
rm -f $(LOG_DIR)/3_*

# ==============================================================================
# _____ ___ _ _ ___ ____ _ _ ___ _ _ ____
# | ___|_ _| \ | |_ _/ ___|| | | |_ _| \ | |/ ___|
# | |_ | || \| || |\___ \| |_| || || \| | | _
# | _| | || |\ || | ___) | _ || || |\ | |_| |
# |_| |___|_| \_|___|____/|_| |_|___|_| \_|\____|
#

6_FINAL_FILE = $(RESULTS_DIR)/6_final.$(STREAM_SYSTEM_EXT)
#finish: $(LOG_DIR)/6_report.log \
# $(RESULTS_DIR)/6_final.v \
# $(6_FINAL_FILE)
finish: $(LOG_DIR)/6_report.log \
$(RESULTS_DIR)/2_floorplan.v

# ==============================================================================

#ifneq ($(USE_FILL),)
#$(RESULTS_DIR)/6_1_fill.def: $(RESULTS_DIR)/5_route.def
# ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/density_fill.tcl -metrics $(LOG_DIR)/6_density_fill.json) 2>&1 | tee $(LOG_DIR)/6_density_fill.log
#else
#$(RESULTS_DIR)/6_1_fill.def: $(RESULTS_DIR)/5_route.def
# cp $< $@
#endif
#
#$(RESULTS_DIR)/6_1_fill.sdc: $(RESULTS_DIR)/5_route.sdc
# cp $< $@
#
#$(LOG_DIR)/6_report.log: $(RESULTS_DIR)/6_1_fill.def $(RESULTS_DIR)/6_1_fill.sdc
# ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/final_report.tcl -metrics $(LOG_DIR)/6_report.json) 2>&1 | tee $(LOG_DIR)/6_report.log
$(LOG_DIR)/6_report.log: $(RESULTS_DIR)/3_place.def $(RESULTS_DIR)/3_place.sdc
($(TIME_CMD) $(OPENROAD_CMD) $(FINAL_REPORT_SCRIPT) -metrics $(LOG_DIR)/6_report.json) 2>&1 | tee $(LOG_DIR)/6_report.log

#
#$(RESULTS_DIR)/6_final.def: $(LOG_DIR)/6_report.log
#
# Merge wrapped macros using Klayout
#-------------------------------------------------------------------------------
#$(WRAPPED_GDSOAS): $(OBJECTS_DIR)/klayout_wrap.lyt $(WRAPPED_LEFS)
# ($(TIME_CMD) klayout -zz -rd design_name=$(basename $(notdir $@)) \
# -rd in_def=$(OBJECTS_DIR)/def/$(notdir $(@:$(STREAM_SYSTEM_EXT)=def)) \
# -rd in_files="$(ADDITIONAL_GDSOAS)" \
# -rd config_file=$(FILL_CONFIG) \
# -rd seal_file="" \
# -rd out_file=$@ \
# -rd tech_file=$(OBJECTS_DIR)/klayout_wrap.lyt \
# -rm $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(LOG_DIR)/6_merge_$(basename $(notdir $@)).log
#
# Merge GDS using Klayout
#-------------------------------------------------------------------------------
#6_1_MERGED_FILE = $(RESULTS_DIR)/6_1_merged.$(STREAM_SYSTEM_EXT)
#$(6_1_MERGED_FILE): $(RESULTS_DIR)/6_final.def $(OBJECTS_DIR)/klayout.lyt $(GDSOAS_FILES) $(WRAPPED_GDSOAS)
# ($(TIME_CMD) stdbuf -o L klayout -zz -rd design_name=$(DESIGN_NAME) \
# -rd in_def=$< \
# -rd in_files="$(GDSOAS_FILES) $(WRAPPED_GDSOAS)" \
# -rd config_file=$(FILL_CONFIG) \
# -rd seal_file="$(SEAL_GDSOAS)" \
# -rd out_file=$@ \
# -rd tech_file=$(OBJECTS_DIR)/klayout.lyt \
# -rm $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(LOG_DIR)/6_1_merge.log
#
#$(RESULTS_DIR)/6_final.v: $(LOG_DIR)/6_report.log
#
#$(6_FINAL_FILE): $(6_1_MERGED_FILE)
# cp $^ $@
#
#drc: $(REPORTS_DIR)/6_drc.lyrdb
#
#$(REPORTS_DIR)/6_drc.lyrdb: $(6_FINAL_FILE) $(KLAYOUT_DRC_FILE)
#ifneq ($(KLAYOUT_DRC_FILE),)
# ($(TIME_CMD) klayout -zz -rd in_gds="$<" \
# -rd report_file=$(abspath $@) \
# -r $(KLAYOUT_DRC_FILE)) 2>&1 | tee $(LOG_DIR)/6_drc.log
# # Hacky way of getting DRV count (don't error on no matches)
# grep -c "<value>" $@ > $(REPORTS_DIR)/6_drc_count.rpt || [[ $$? == 1 ]]
#else
# echo "DRC not supported on this platform" > $@
#endif
#
#$(RESULTS_DIR)/6_final.cdl: $(RESULTS_DIR)/6_final.v
# ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/cdl.tcl) 2>&1 | tee $(LOG_DIR)/6_cdl.log
#
#$(OBJECTS_DIR)/6_final_concat.cdl: $(RESULTS_DIR)/6_final.cdl $(CDL_FILE)
# cat $^ > $@
#
#lvs: $(RESULTS_DIR)/6_lvs.lvsdb
#
#$(RESULTS_DIR)/6_lvs.lvsdb: $(6_FINAL_FILE) $(KLAYOUT_LVS_FILE) $(OBJECTS_DIR)/6_final_concat.cdl
#ifneq ($(KLAYOUT_LVS_FILE),)
# ($(TIME_CMD) klayout -b -rd in_gds="$<" \
# -rd cdl_file=$(abspath $(OBJECTS_DIR)/6_final_concat.cdl) \
# -rd report_file=$(abspath $@) \
# -r $(KLAYOUT_LVS_FILE)) 2>&1 | tee $(LOG_DIR)/6_lvs.log
#else
# echo "LVS not supported on this platform" > $@
#endif

clean_finish:
rm -rf $(RESULTS_DIR)/6_*.gds $(RESULTS_DIR)/6_*.oas $(RESULTS_DIR)/6_*.def $(RESULTS_DIR)/6_*.v $(RESULTS_DIR)/6_*.sdc
rm -rf $(REPORTS_DIR)/6_*.rpt
rm -f $(LOG_DIR)/6_*


# ==============================================================================
# __ __ ___ ____ ____
# | \/ |_ _/ ___| / ___|
# | |\/| || |\___ \| |
# | | | || | ___) | |___
# |_| |_|___|____/ \____|
#
# ==============================================================================

all: $(SDC_FILE) $(WRAPPED_LIBS) $(DONT_USE_LIBS) $(OBJECTS_DIR)/klayout.lyt $(WRAPPED_GDSOAS)
mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR)
($(TIME_CMD) $(OPENROAD_CMD) $(RUN_ALL_SCRIPT) -metrics $(LOG_DIR)/run_all.json) 2>&1 | tee $(LOG_DIR)/run_all.log

clean:
@echo
@echo "Make clean disabled."
@echo "Use make clean_all or clean individual steps:"
@echo " clean_synth clean_floorplan clean_place clean_cts clean_route clean_finish"
@echo

clean_all: clean_synth clean_floorplan clean_place clean_cts clean_route clean_finish
rm -rf $(OBJECTS_DIR)

nuke: clean_test clean_issues
rm -rf ./results ./logs ./reports ./objects
rm -rf layer_*.mps macrocell.list *best.plt *_pdn.def dummy.guide
rm -rf *.rpt *.rpt.old *.def.v pin_dumper.log
rm -rf versions.txt


# DEF/GDS/OAS viewer shortcuts
#-------------------------------------------------------------------------------
RESULTS_DEF = $(notdir $(sort $(wildcard $(RESULTS_DIR)/*.def)))
RESULTS_GDS = $(notdir $(sort $(wildcard $(RESULTS_DIR)/*.gds)))
RESULTS_OAS = $(notdir $(sort $(wildcard $(RESULTS_DIR)/*.oas)))
$(foreach file,$(RESULTS_DEF) $(RESULTS_GDS) $(RESULTS_OAS),klayout_$(file)): klayout_%: $(OBJECTS_DIR)/klayout.lyt
klayout -nn $(OBJECTS_DIR)/klayout.lyt $(RESULTS_DIR)/$*

gui_final: gui_6_final.def

$(foreach file,$(RESULTS_DEF),gui_$(file)): gui_%:
DEF_FILE=$(RESULTS_DIR)/$* $(OPENROAD_NO_EXIT_CMD) -gui $(SCRIPTS_DIR)/gui.tcl

# Utilities
#-------------------------------------------------------------------------------
include $(UTILS_DIR)/utils.mk
export PRIVATE_DIR = ../../private_tool_scripts
-include $(PRIVATE_DIR)/util/utils.mk

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build/openroad/allrams.log
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14
build/openroad/config.mk
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@ -25,4 +25,16 @@ export SYNTH_MAX_TRAN ?= 100


export REPORT_SLACK_MAX_PATHS ?= 100 export REPORT_SLACK_MAX_PATHS ?= 100



# ----------------------------------------------------------------------------------
# ----------------------------------------------------------------------------------
# CTS

# forget about this for now - occurred when added dffram dir/caches. anton says hold misses are fake anyway :)
# do i need something else from dffram build?
# Repair hold violations...
# [INFO RSZ-0046] Found 60472 endpoints with hold violations.
# [WARNING RSZ-0066] Unable to repair all hold violations.
# [INFO RSZ-0032] Inserted 213923 hold buffers.
# [ERROR DPL-0019] detailed placement failed on hold33177
# continue if cts wants to barf...
export WTF_CTS_IGNORE_HOLD_MISSES = 1

24
build/openroad/constraint.sdc
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@ -1,23 +1,29 @@
set clk_name clk # A2P single-core with DFFRAM gpr, icdir, icdata, dcdir, dcdata
# make it easy
set clk_period 50.0

set input_delay_value 1
set output_delay_value 1


# ----------------------------------------------------------------------------------
# define clock # define clock

set clk_name clk
# set clk_period 50.0 ;# make it easy for or
set clk_period 10.0
puts "\[WTF\] clk_period=$clk_period"

set clkPort [get_ports $clk_name] set clkPort [get_ports $clk_name]
create_clock $clkPort -name clk -period $clk_period create_clock $clkPort -name clk -period $clk_period


# ----------------------------------------------------------------------------------
# apply clock to ins and outs # apply clock to ins and outs

set input_delay_value 0.0
set output_delay_value 0.0 ;# what is this? rat? or period-rat? i think 0 is 'easiest'

set clk_index [lsearch [all_inputs] $clkPort] set clk_index [lsearch [all_inputs] $clkPort]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_index $clk_index] set all_inputs_wo_clk [lreplace [all_inputs] $clk_index $clk_index]
set_input_delay $input_delay_value -clock [get_clocks clk] $all_inputs_wo_clk set_input_delay $input_delay_value -clock [get_clocks clk] $all_inputs_wo_clk
set_output_delay $output_delay_value -clock [get_clocks clk] [all_outputs] set_output_delay $output_delay_value -clock [get_clocks clk] [all_outputs]


# ----------------------------------------------------------------------------------
# false paths # false paths

set_false_path -from [get_ports {reset}] -to [get_clocks clk] set_false_path -from [get_ports {reset}] -to [get_clocks clk]


#wtf - is this the dc write path? lots of fo
#set_false_path -from [get_nets {dBusWB_ACK}]
#causes [ERROR STA-0467] unsupported object type Net

393
build/openroad/log.py
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@ -0,0 +1,393 @@
# general text parser

import os
import sys
from time import sleep
import glob
import json
import re
#import jsonpickle

# config
# file (inc. glob)
# list of searches: type (re, etc), singe/multiline, text, template

class Spec:
def __init__(self):
self.val = None
self.multiline = False
self.re = False
self.post = None # postprocessor function
self.ci = False # case-insensitive
self.flags = 0 # re flags
self.matchOnly = False # return re match, or whole result (if not multiline)
self.before = 0
self.after = 0
# start from prev?
# callback for every match?
self.search = False # use re.search instead of re.match

class Config:
def __init__(self):
self.specs = None
self.title = None

def toJson(self):
return json.dumps(self, default=lambda o: o.__dict__)

class Log:

def __init__(self, config=None):
self.config = config

# process all matching files, or newest only
def processGlob(self, g, spec, newest=False):
files = glob.glob(g)
if newest:
files = [max(files, key=os.path.getctime)]
for f in files:
self.processFile(f, spec)

# read file
def processFile(self, fn, spec):
contents = None
lines = None

# process spec list in order
results = []
for s in spec:

if s.multiline and contents is None:
with open(fn, 'r') as f:
contents = f.read()
elif lines is None:
lines = []
with open(fn, 'r') as f:
for l in f:
lines.append(l.rstrip('\n'))

v = []
if s.re:
if s.multiline:
r = re.findall(s.val, contents, s.flags)
for i in range(len(r)):
v.append(r[i])
else:
for i in range(len(lines)):
l = lines[i]
matchFn = re.match if not s.search else re.search
res = matchFn(s.val, l, s.flags)
if res is not None:
if s.matchOnly:
v.append(res.groups())
else:
if s.before == -1:
for j in range(0, i):
v.append(lines[j])
elif s.before > 0:
for j in range(max(0, i-s.before), i):
v.append(lines[j])
v.append(l)
if s.after == -1:
for j in range(i+1, len(lines)):
v.append(lines[j])
elif s.after > 0:
for j in range(i+1, i+1+s.after):
v.append(lines[j])

else:
if s.multiline:
p = 0
while p < len(contents):
p1 = contents.find(s.val, p)
if p1 == -1:
break
v.append(p1)
p += len(p1)
else:
for i in range(len(lines)):
l = lines[i]
if l.find(s.val) != -1:
if s.before == -1:
for j in range(0, i):
v.append(lines[j])
elif s.before > 0:
for j in range(max(0, i-s.before), i):
v.append(lines[j])
v.append(l)
if s.after == -1:
for j in range(i+1, len(lines)):
v.append(lines[j])
elif s.after > 0:
for j in range(i+1, i+1+s.after):
v.append(lines[j])

results.append(v)

return results

if __name__ == '__main__':

import os.path, time
import argparse
parser = argparse.ArgumentParser()
parser.add_argument('logFile')
parser.add_argument('-l', '--loops', type=int, dest='loops', default=200, help='loops to run; default=200')
parser.add_argument('-m', '--move', type=int, dest='move', default=10, help='rate of movement (1/n iterations); default=10')
parser.add_argument('--test', dest='testVal', default=None, help='test value')
args = parser.parse_args()

logDir = args.logFile

# openroad testing

log = Log()

# --------------------

logFile = logDir + '/1_1_yosys.log'
print('Report: ' + logFile)
print('')

s0 = Spec()
s0.val = r'^Yosys .* \(git sha1'
s0.re = True

s1 = Spec()
s1.val = r'\n(30\. .*)'
s1.re = True
s1.multiline = True
s1.flags = re.DOTALL

specs = [s0, s1]
config = Config()
config.specs = specs

res = log.processFile(logFile, config.specs)
for i in range(len(res)):
for l in res[i]:
print(l)
print('')

print()
print('*** Warnings ***')
print()

s0 = Spec()
s0.val = r'(Warning:.*)'
s0.re = True
config = Config()
config.specs = [s0]
res = log.processFile(logFile, config.specs)
for i in range(len(res)):
for l in res[i]:
print(l)
print('')

s0 = Spec()
s0.val = r'(Error:.*)'
s0.re = True
config = Config()
config.specs = [s0]
res = log.processFile(logFile, config.specs)

found = False
for i in range(len(res)):
for l in res[i]:
if not found:
print()
print('*** Errors ***')
print()
found = True
print(l)
print('')

# --------------------
logFile = logDir + '/2_1_floorplan.log'
print('Report: ' + logFile)
print('')

s0 = Spec()
s0.val = r'\n(Design area .*)'
s0.re = True
s0.multiline = True
s0.flags = re.DOTALL

config = Config()
config.specs = [s0]

res = log.processFile(logFile, config.specs)
for i in range(len(res)):
for l in res[i]:
print(l)
print('')

# --------------------
logFile = logDir + '/2_2_floorplan_io.log'
print('Report: ' + logFile)
print('')

s0 = Spec()
s0.val = r'\n\[INFO ODB-0134\].*?\n(.*)'
s0.re = True
s0.multiline = True
s0.flags = re.DOTALL

config = Config()
config.specs = [s0]

res = log.processFile(logFile, config.specs)
for i in range(len(res)):
for l in res[i]:
print(l)
print('')

# --------------------
logFile = logDir + '/2_3_tdms_place.log'
print('Report: ' + logFile)
print('')

s0 = Spec()
s0.val = r'\n\[INFO ODB-0134\].*?\n(.*)'
s0.re = True
s0.multiline = True
s0.flags = re.DOTALL

config = Config()
config.specs = [s0]

res = log.processFile(logFile, config.specs)
for i in range(len(res)):
for l in res[i]:
print(l)
print('')

# --------------------
logFile = logDir + '/2_4_mplace.log'
print('Report: ' + logFile)
print('')

s0 = Spec()
s0.val = r'\n\[INFO ODB-0134\].*?\n(.*)'
s0.re = True
s0.multiline = True
s0.flags = re.DOTALL

config = Config()
config.specs = [s0]

res = log.processFile(logFile, config.specs)
for i in range(len(res)):
for l in res[i]:
print(l)
print('')

# --------------------
logFile = logDir + '/2_5_tapcell.log'
print('Report: ' + logFile)
print('')

s0 = Spec()
s0.val = r'\n\[INFO TAP-0005\].*?\n(.*)'
s0.re = True
s0.multiline = True
s0.flags = re.DOTALL

config = Config()
config.specs = [s0]

res = log.processFile(logFile, config.specs)
for i in range(len(res)):
for l in res[i]:
print(l)
print('')

# --------------------
logFile = logDir + '/2_6_pdn.log'
print('Report: ' + logFile)
print('')

s0 = Spec()
s0.val = r'\n\[INFO PDN-0015\].*?\n(.*)'
s0.re = True
s0.multiline = True
s0.flags = re.DOTALL

config = Config()
config.specs = [s0]

res = log.processFile(logFile, config.specs)
for i in range(len(res)):
for l in res[i]:
print(l)
print('')

quit()

# python makes this hard for even trivial objects
print('Writing config.json...')

configJson = json.dumps(config, default=lambda x: x.__dict__)
#configJson = jsonpickle.encode(config)
print(configJson)
#quit()
#
#configJson = json.dumps(config.toJson(), indent=2)
with open('config.json', 'w') as configFile:
configFile.write(configJson)
configFile.close()

print('Reading config.json...')
print('')

print('string')
with open('config.json', 'r') as configFile:
print(configFile.read())
configFile.close()

print('loads')
with open('config.json', 'r') as configFile:
config = json.loads(configFile.read())
print(config)
configFile.close()

res = log.processFile(logFile, config.specs)
for i in range(len(res)):
for l in res[i]:
print(l)
print('')

# fpga
s0 = Spec()
s0.val = r'.*Command.*-hierarchical (.*)\*.*'
s0.re = True
s0.matchOnly = True

specs = [s0]
log = Log()
res = log.processFile(logFile, specs)

comps = []
for r in res:
for i in r:
comps.append({
'name': i[0],
'luts': -1
})

s0.val = r'.*Slice LUTs.*?\|(.*?)\|'

res = log.processFile(logFile, specs)

for r in res:
for i in range(len(r)):
comps[i]['luts'] = r[i][0]


mod = time.ctime(os.path.getmtime(logFile))
print(f"report: {logFile} [{mod}]")
for i in range(len(comps)):
print(f"{comps[i]['name']:16}: {comps[i]['luts']:>7}")


quit()

0
build/openroad/logs/1_1_yosys.log → build/openroad/logs/clk_100/1_1_yosys.log
Unescape Escape View File

0
build/openroad/logs/2_1_floorplan.json → build/openroad/logs/clk_100/2_1_floorplan.json
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335
build/openroad/logs/clk_100/2_1_floorplan.log
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@ -0,0 +1,335 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
number instances in verilog is 86814
[INFO IFP-0001] Added 1535 rows of 10390 sites.
[INFO RSZ-0026] Removed 8252 buffers.
Default units for flow
time 1ns
capacitance 1pF
resistance 1kohm
voltage 1v
current 1mA
power 1nW
distance 1um

==========================================================================
floorplan final report_checks -path_delay min
--------------------------------------------------------------------------
Startpoint: externalResetVector[1] (input port clocked by clk)
Endpoint: _145458_ (removal check against rising-edge clock clk)
Path Group: **async_default**
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 0.00 1.00 v externalResetVector[1] (in)
2 0.00 externalResetVector[1] (net)
0.00 0.00 1.00 v _122265_/B (sky130_fd_sc_hd__nand2_1)
0.05 0.05 1.05 ^ _122265_/Y (sky130_fd_sc_hd__nand2_1)
1 0.00 _000016_ (net)
0.05 0.01 1.06 ^ _145458_/SET_B (sky130_fd_sc_hd__dfbbp_1)
1.06 data arrival time

0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _145458_/CLK (sky130_fd_sc_hd__dfbbp_1)
0.11 0.11 library removal time
0.11 data required time
-----------------------------------------------------------------------------
0.11 data required time
-1.06 data arrival time
-----------------------------------------------------------------------------
0.95 slack (MET)


Startpoint: _144888_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _122419_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _144888_/CLK (sky130_fd_sc_hd__dfxtp_1)
0.05 0.29 0.29 ^ _144888_/Q (sky130_fd_sc_hd__dfxtp_1)
2 0.00 dataCache_1_.io_mem_cmd_payload_data[0] (net)
0.05 0.00 0.29 ^ _122419_/D (sky130_fd_sc_hd__dfxtp_1)
0.29 data arrival time

0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _122419_/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.04 -0.04 library hold time
-0.04 data required time
-----------------------------------------------------------------------------
-0.04 data required time
-0.29 data arrival time
-----------------------------------------------------------------------------
0.33 slack (MET)



==========================================================================
floorplan final report_checks -path_delay max
--------------------------------------------------------------------------
Startpoint: externalResetVector[1] (input port clocked by clk)
Endpoint: _145458_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 0.00 1.00 ^ externalResetVector[1] (in)
2 0.00 externalResetVector[1] (net)
0.00 0.00 1.00 ^ _122230_/A_N (sky130_fd_sc_hd__nand2b_1)
0.04 0.07 1.07 ^ _122230_/Y (sky130_fd_sc_hd__nand2b_1)
1 0.00 _000015_ (net)
0.04 0.00 1.07 ^ _145458_/RESET_B (sky130_fd_sc_hd__dfbbp_1)
1.07 data arrival time

0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ _145458_/CLK (sky130_fd_sc_hd__dfbbp_1)
-0.07 9.93 library recovery time
9.93 data required time
-----------------------------------------------------------------------------
9.93 data required time
-1.07 data arrival time
-----------------------------------------------------------------------------
8.85 slack (MET)


Startpoint: _143560_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _135893_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _143560_/CLK (sky130_fd_sc_hd__dfxtp_1)
0.15 0.36 0.36 ^ _143560_/Q (sky130_fd_sc_hd__dfxtp_1)
5 0.01 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] (net)
0.15 0.01 0.37 ^ _061283_/B (sky130_fd_sc_hd__xor2_1)
0.15 0.18 0.55 ^ _061283_/X (sky130_fd_sc_hd__xor2_1)
1 0.00 _025146_ (net)
0.15 0.01 0.56 ^ _061285_/C (sky130_fd_sc_hd__nor4_2)
0.06 0.08 0.64 v _061285_/Y (sky130_fd_sc_hd__nor4_2)
4 0.01 _025148_ (net)
0.06 0.00 0.64 v _061286_/B (sky130_fd_sc_hd__and2_0)
0.12 0.22 0.86 v _061286_/X (sky130_fd_sc_hd__and2_0)
4 0.01 _025149_ (net)
0.12 0.01 0.86 v _077118_/A1 (sky130_fd_sc_hd__a21oi_2)
3.52 2.65 3.51 ^ _077118_/Y (sky130_fd_sc_hd__a21oi_2)
117 0.31 _029150_ (net)
3.52 0.00 3.51 ^ _079640_/A1 (sky130_fd_sc_hd__o21a_1)
192.27 134.78 138.29 ^ _079640_/X (sky130_fd_sc_hd__o21a_1)
5371 21.05 _029825_ (net)
192.27 0.00 138.30 ^ _079726_/B (sky130_fd_sc_hd__nor2_1)
167.08 431.17 569.47 v _079726_/Y (sky130_fd_sc_hd__nor2_1)
363 0.85 _029911_ (net)
167.08 0.00 569.47 v _098672_/B2 (sky130_fd_sc_hd__a221oi_1)
21.53 43.69 613.16 ^ _098672_/Y (sky130_fd_sc_hd__a221oi_1)
1 0.00 _048845_ (net)
21.53 0.00 613.16 ^ _098673_/B1 (sky130_fd_sc_hd__o21ai_0)
11.56 1.30 614.46 v _098673_/Y (sky130_fd_sc_hd__o21ai_0)
1 0.00 _048846_ (net)
11.56 0.00 614.47 v _098688_/A2 (sky130_fd_sc_hd__a311oi_1)
1.14 2.88 617.35 ^ _098688_/Y (sky130_fd_sc_hd__a311oi_1)
1 0.00 _048861_ (net)
1.14 0.00 617.35 ^ _098689_/D1 (sky130_fd_sc_hd__a2111oi_0)
0.21 0.14 617.49 v _098689_/Y (sky130_fd_sc_hd__a2111oi_0)
1 0.00 _048862_ (net)
0.21 0.00 617.49 v _098690_/B1 (sky130_fd_sc_hd__a41o_1)
0.28 0.26 617.75 v _098690_/X (sky130_fd_sc_hd__a41o_1)
1 0.00 _048863_ (net)
0.28 0.00 617.76 v _098691_/C1 (sky130_fd_sc_hd__a211oi_1)
0.20 0.25 618.01 ^ _098691_/Y (sky130_fd_sc_hd__a211oi_1)
1 0.00 _048864_ (net)
0.20 0.00 618.01 ^ _099021_/B1 (sky130_fd_sc_hd__a311o_1)
0.05 0.14 618.15 ^ _099021_/X (sky130_fd_sc_hd__a311o_1)
1 0.00 _013487_ (net)
0.05 0.00 618.15 ^ _135893_/D (sky130_fd_sc_hd__dfxtp_1)
618.15 data arrival time

0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ _135893_/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.06 9.94 library setup time
9.94 data required time
-----------------------------------------------------------------------------
9.94 data required time
-618.15 data arrival time
-----------------------------------------------------------------------------
-608.22 slack (VIOLATED)



==========================================================================
floorplan final report_checks -unconstrained
--------------------------------------------------------------------------
Startpoint: externalResetVector[1] (input port clocked by clk)
Endpoint: _145458_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 0.00 1.00 ^ externalResetVector[1] (in)
2 0.00 externalResetVector[1] (net)
0.00 0.00 1.00 ^ _122230_/A_N (sky130_fd_sc_hd__nand2b_1)
0.04 0.07 1.07 ^ _122230_/Y (sky130_fd_sc_hd__nand2b_1)
1 0.00 _000015_ (net)
0.04 0.00 1.07 ^ _145458_/RESET_B (sky130_fd_sc_hd__dfbbp_1)
1.07 data arrival time

0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ _145458_/CLK (sky130_fd_sc_hd__dfbbp_1)
-0.07 9.93 library recovery time
9.93 data required time
-----------------------------------------------------------------------------
9.93 data required time
-1.07 data arrival time
-----------------------------------------------------------------------------
8.85 slack (MET)


Startpoint: _143560_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _135893_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _143560_/CLK (sky130_fd_sc_hd__dfxtp_1)
0.15 0.36 0.36 ^ _143560_/Q (sky130_fd_sc_hd__dfxtp_1)
5 0.01 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] (net)
0.15 0.01 0.37 ^ _061283_/B (sky130_fd_sc_hd__xor2_1)
0.15 0.18 0.55 ^ _061283_/X (sky130_fd_sc_hd__xor2_1)
1 0.00 _025146_ (net)
0.15 0.01 0.56 ^ _061285_/C (sky130_fd_sc_hd__nor4_2)
0.06 0.08 0.64 v _061285_/Y (sky130_fd_sc_hd__nor4_2)
4 0.01 _025148_ (net)
0.06 0.00 0.64 v _061286_/B (sky130_fd_sc_hd__and2_0)
0.12 0.22 0.86 v _061286_/X (sky130_fd_sc_hd__and2_0)
4 0.01 _025149_ (net)
0.12 0.01 0.86 v _077118_/A1 (sky130_fd_sc_hd__a21oi_2)
3.52 2.65 3.51 ^ _077118_/Y (sky130_fd_sc_hd__a21oi_2)
117 0.31 _029150_ (net)
3.52 0.00 3.51 ^ _079640_/A1 (sky130_fd_sc_hd__o21a_1)
192.27 134.78 138.29 ^ _079640_/X (sky130_fd_sc_hd__o21a_1)
5371 21.05 _029825_ (net)
192.27 0.00 138.30 ^ _079726_/B (sky130_fd_sc_hd__nor2_1)
167.08 431.17 569.47 v _079726_/Y (sky130_fd_sc_hd__nor2_1)
363 0.85 _029911_ (net)
167.08 0.00 569.47 v _098672_/B2 (sky130_fd_sc_hd__a221oi_1)
21.53 43.69 613.16 ^ _098672_/Y (sky130_fd_sc_hd__a221oi_1)
1 0.00 _048845_ (net)
21.53 0.00 613.16 ^ _098673_/B1 (sky130_fd_sc_hd__o21ai_0)
11.56 1.30 614.46 v _098673_/Y (sky130_fd_sc_hd__o21ai_0)
1 0.00 _048846_ (net)
11.56 0.00 614.47 v _098688_/A2 (sky130_fd_sc_hd__a311oi_1)
1.14 2.88 617.35 ^ _098688_/Y (sky130_fd_sc_hd__a311oi_1)
1 0.00 _048861_ (net)
1.14 0.00 617.35 ^ _098689_/D1 (sky130_fd_sc_hd__a2111oi_0)
0.21 0.14 617.49 v _098689_/Y (sky130_fd_sc_hd__a2111oi_0)
1 0.00 _048862_ (net)
0.21 0.00 617.49 v _098690_/B1 (sky130_fd_sc_hd__a41o_1)
0.28 0.26 617.75 v _098690_/X (sky130_fd_sc_hd__a41o_1)
1 0.00 _048863_ (net)
0.28 0.00 617.76 v _098691_/C1 (sky130_fd_sc_hd__a211oi_1)
0.20 0.25 618.01 ^ _098691_/Y (sky130_fd_sc_hd__a211oi_1)
1 0.00 _048864_ (net)
0.20 0.00 618.01 ^ _099021_/B1 (sky130_fd_sc_hd__a311o_1)
0.05 0.14 618.15 ^ _099021_/X (sky130_fd_sc_hd__a311o_1)
1 0.00 _013487_ (net)
0.05 0.00 618.15 ^ _135893_/D (sky130_fd_sc_hd__dfxtp_1)
618.15 data arrival time

0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ _135893_/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.06 9.94 library setup time
9.94 data required time
-----------------------------------------------------------------------------
9.94 data required time
-618.15 data arrival time
-----------------------------------------------------------------------------
-608.22 slack (VIOLATED)



==========================================================================
floorplan final report_tns
--------------------------------------------------------------------------
tns -159483.34

==========================================================================
floorplan final report_wns
--------------------------------------------------------------------------
wns -608.22

==========================================================================
floorplan final report_worst_slack
--------------------------------------------------------------------------
worst slack -608.22

==========================================================================
floorplan final report_clock_skew
--------------------------------------------------------------------------
Clock clk
Latency CRPR Skew
_145458_/CLK ^
0.00
_143514_/CLK ^
0.00 0.00 0.00


==========================================================================
floorplan final report_power
--------------------------------------------------------------------------
Group Internal Switching Leakage Total
Power Power Power Power
----------------------------------------------------------------
Sequential 1.00e-01 3.00e-03 2.04e-07 1.03e-01 57.4%
Combinational 6.97e-02 6.82e-03 1.65e-07 7.65e-02 42.6%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 1.70e-01 9.82e-03 3.69e-07 1.80e-01 100.0%
94.5% 5.5% 0.0%

==========================================================================
floorplan final report_design_area
--------------------------------------------------------------------------
Design area 941804 u^2 5% utilization.

Elapsed time: 0:11.27[h:]min:sec. CPU time: user 11.13 sys 0.10 (99%). Peak memory: 332320KB.

0
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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_1_floorplan.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 78562 components and 443582 component-terminals.
[INFO ODB-0133] Created 77777 nets and 286452 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_1_floorplan.def
Found 0 macro blocks.
Using 1u default distance from corners.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0007] Random pin placement.
Elapsed time: 0:01.14[h:]min:sec. CPU time: user 1.05 sys 0.04 (96%). Peak memory: 190396KB.

0
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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_2_floorplan_io.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 78562 components and 443582 component-terminals.
[INFO ODB-0133] Created 77777 nets and 286452 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_2_floorplan_io.def
No macros found: Skipping global_placement
Elapsed time: 0:01.20[h:]min:sec. CPU time: user 1.10 sys 0.05 (96%). Peak memory: 188568KB.

0
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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_3_floorplan_tdms.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 78562 components and 443582 component-terminals.
[INFO ODB-0133] Created 77777 nets and 286452 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_3_floorplan_tdms.def
No macros found: Skipping macro_placement
Elapsed time: 0:01.19[h:]min:sec. CPU time: user 1.11 sys 0.04 (97%). Peak memory: 187752KB.

0
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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_4_floorplan_macro.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 78562 components and 443582 component-terminals.
[INFO ODB-0133] Created 77777 nets and 286452 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_4_floorplan_macro.def
[WARNING TAP-0014] endcap_cpp option is deprecated.
[INFO TAP-0001] Found 0 macro blocks.
[INFO TAP-0002] Original rows: 1535
[INFO TAP-0003] Created 0 rows for a total of 1535 rows.
[INFO TAP-0005] Inserted 265901 tapcells.
Elapsed time: 0:01.69[h:]min:sec. CPU time: user 1.55 sys 0.10 (97%). Peak memory: 225260KB.

0
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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_5_floorplan_tapcell.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 344463 components and 975384 component-terminals.
[INFO ODB-0133] Created 77777 nets and 286452 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_5_floorplan_tapcell.def
[INFO PDN-0016] Power Delivery Network Generator: Generating PDN
config: ./platforms/sky130hd/pdn.cfg
[INFO PDN-0008] Design name is A2P_WB.
[INFO PDN-0009] Reading technology data.
[INFO PDN-0011] ****** INFO ******
Type: stdcell, grid
Stdcell Rails
Layer: met1 - width: 0.480 pitch: 5.440 offset: 0.000
Straps
Layer: met4 - width: 1.600 pitch: 27.140 offset: 13.570
Layer: met5 - width: 1.600 pitch: 27.200 offset: 13.600
Connect: {met1 met4} {met4 met5}
Type: macro, CORE_macro_grid_1
Macro orientation: R0 R180 MX MY
Connect: {met4_PIN_ver met5}
Type: macro, CORE_macro_grid_2
Macro orientation: R90 R270 MXR90 MYR90
Connect: {met4_PIN_hor met5}
[INFO PDN-0012] **** END INFO ****
[INFO PDN-0013] Inserting stdcell grid - grid.
[INFO PDN-0015] Writing to database.
Elapsed time: 0:31.86[h:]min:sec. CPU time: user 30.77 sys 1.04 (99%). Peak memory: 3428312KB.

0
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492
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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_floorplan.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 344463 components and 975384 component-terminals.
[INFO ODB-0132] Created 2 special nets and 688926 connections.
[INFO ODB-0133] Created 77777 nets and 286452 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_floorplan.def
[INFO GPL-0002] DBU: 1000
[INFO GPL-0003] SiteSize: 460 2720
[INFO GPL-0004] CoreAreaLxLy: 210220 212160
[INFO GPL-0005] CoreAreaUxUy: 4989620 4387360
[INFO GPL-0006] NumInstances: 344463
[INFO GPL-0007] NumPlaceInstances: 78562
[INFO GPL-0008] NumFixedInstances: 265901
[INFO GPL-0009] NumDummyInstances: 0
[INFO GPL-0010] NumNets: 77777
[INFO GPL-0011] NumPins: 286706
[INFO GPL-0012] DieAreaLxLy: 0 0
[INFO GPL-0013] DieAreaUxUy: 5200000 4609140
[INFO GPL-0014] CoreAreaLxLy: 210220 212160
[INFO GPL-0015] CoreAreaUxUy: 4989620 4387360
[INFO GPL-0016] CoreArea: 19954950880000
[INFO GPL-0017] NonPlaceInstsArea: 332695331200
[INFO GPL-0018] PlaceInstsArea: 1728178710400
[INFO GPL-0019] Util(%): 8.81
[INFO GPL-0020] StdInstsArea: 1728178710400
[INFO GPL-0021] MacroInstsArea: 0
[InitialPlace] Iter: 1 CG Error: 0.00850115 HPWL: 1578098575
[InitialPlace] Iter: 2 CG Error: 0.00011517 HPWL: 1157650885
[InitialPlace] Iter: 3 CG Error: 0.00002250 HPWL: 1124443183
[InitialPlace] Iter: 4 CG Error: 0.00000630 HPWL: 1114752247
[InitialPlace] Iter: 5 CG Error: 0.00000383 HPWL: 1111906825
[INFO GPL-0031] FillerInit: NumGCells: 536760
[INFO GPL-0032] FillerInit: NumGNets: 77777
[INFO GPL-0033] FillerInit: NumGPins: 286706
[INFO GPL-0023] TargetDensity: 0.60
[INFO GPL-0024] AveragePlaceInstArea: 21997641
[INFO GPL-0025] IdealBinArea: 36662732
[INFO GPL-0026] IdealBinCnt: 544284
[INFO GPL-0027] TotalBinArea: 19954950880000
[INFO GPL-0028] BinCnt: 512 512
[INFO GPL-0029] BinSize: 9335 8155
[INFO GPL-0030] NumBins: 262144
[NesterovSolve] Iter: 1 overflow: 0.996147 HPWL: 548926693
[NesterovSolve] Iter: 10 overflow: 0.987203 HPWL: 632425412
[NesterovSolve] Iter: 20 overflow: 0.979323 HPWL: 729609532
[NesterovSolve] Iter: 30 overflow: 0.977077 HPWL: 725711076
[NesterovSolve] Iter: 40 overflow: 0.976295 HPWL: 723570420
[NesterovSolve] Iter: 50 overflow: 0.975941 HPWL: 719413738
[NesterovSolve] Iter: 60 overflow: 0.975887 HPWL: 713447664
[NesterovSolve] Iter: 70 overflow: 0.975689 HPWL: 712095673
[NesterovSolve] Iter: 80 overflow: 0.97586 HPWL: 713423398
[NesterovSolve] Iter: 90 overflow: 0.975927 HPWL: 711437993
[NesterovSolve] Iter: 100 overflow: 0.975856 HPWL: 710835720
[NesterovSolve] Iter: 110 overflow: 0.975769 HPWL: 710505240
[NesterovSolve] Iter: 120 overflow: 0.97577 HPWL: 710471259
[NesterovSolve] Iter: 130 overflow: 0.975741 HPWL: 710755191
[NesterovSolve] Iter: 140 overflow: 0.975628 HPWL: 712647202
[NesterovSolve] Iter: 150 overflow: 0.975677 HPWL: 719704294
[NesterovSolve] Iter: 160 overflow: 0.975574 HPWL: 738130373
[NesterovSolve] Iter: 170 overflow: 0.975251 HPWL: 766609491
[NesterovSolve] Iter: 180 overflow: 0.974668 HPWL: 800267501
[NesterovSolve] Iter: 190 overflow: 0.973951 HPWL: 836128766
[NesterovSolve] Iter: 200 overflow: 0.972519 HPWL: 875331943
[NesterovSolve] Iter: 210 overflow: 0.970312 HPWL: 923308764
[NesterovSolve] Iter: 220 overflow: 0.966912 HPWL: 989544951
[NesterovSolve] Iter: 230 overflow: 0.960995 HPWL: 1089566797
[NesterovSolve] Iter: 240 overflow: 0.951896 HPWL: 1237925605
[NesterovSolve] Iter: 250 overflow: 0.937812 HPWL: 1432077509
[NesterovSolve] Iter: 260 overflow: 0.919668 HPWL: 1662080946
[NesterovSolve] Iter: 270 overflow: 0.897175 HPWL: 1869229426
[NesterovSolve] Iter: 280 overflow: 0.872271 HPWL: 1975668436
[NesterovSolve] Iter: 290 overflow: 0.846411 HPWL: 1953953181
[NesterovSolve] Iter: 300 overflow: 0.814004 HPWL: 1985306775
[NesterovSolve] Iter: 310 overflow: 0.77601 HPWL: 2340307070
[NesterovSolve] Iter: 320 overflow: 0.745222 HPWL: 2599045777
[NesterovSolve] Iter: 330 overflow: 0.717832 HPWL: 2395080038
[NesterovSolve] Iter: 340 overflow: 0.672248 HPWL: 2645284819
[NesterovSolve] Iter: 350 overflow: 0.649095 HPWL: 2466165492
[NesterovSolve] Iter: 360 overflow: 0.600172 HPWL: 2576003652
[NesterovSolve] Snapshot saved at iter = 360
[NesterovSolve] Iter: 370 overflow: 0.563795 HPWL: 2453239622
[NesterovSolve] Iter: 380 overflow: 0.513661 HPWL: 2455737805
[NesterovSolve] Iter: 390 overflow: 0.469066 HPWL: 2455148275
[NesterovSolve] Iter: 400 overflow: 0.433779 HPWL: 2380517690
[NesterovSolve] Iter: 410 overflow: 0.392919 HPWL: 2342947358
[NesterovSolve] Iter: 420 overflow: 0.354071 HPWL: 2309462197
[NesterovSolve] Iter: 430 overflow: 0.32213 HPWL: 2286557575
[NesterovSolve] Iter: 440 overflow: 0.293149 HPWL: 2274658447
[NesterovSolve] Iter: 450 overflow: 0.26558 HPWL: 2270686982
[NesterovSolve] Iter: 460 overflow: 0.239111 HPWL: 2270607675
[NesterovSolve] Iter: 470 overflow: 0.212833 HPWL: 2274828173
[INFO GPL-0075] Routability numCall: 1 inflationIterCnt: 1 bloatIterCnt: 0
[INFO GRT-0020] Min routing layer: met1
[INFO GRT-0021] Max routing layer: met5
[INFO GRT-0022] Global adjustment: 0%
[INFO GRT-0023] Grid origin: (0, 0)
[WARNING GRT-0043] No OR_DEFAULT vias defined.
[INFO GRT-0224] Chose via L1M1_PR as default.
[INFO GRT-0224] Chose via M1M2_PR as default.
[INFO GRT-0224] Chose via M2M3_PR as default.
[INFO GRT-0224] Chose via M3M4_PR as default.
[INFO GRT-0224] Chose via M4M5_PR as default.
[INFO GRT-0088] Layer li1 Track-Pitch = 0.4600 line-2-Via Pitch: 0.3400
[INFO GRT-0088] Layer met1 Track-Pitch = 0.3400 line-2-Via Pitch: 0.3400
[INFO GRT-0088] Layer met2 Track-Pitch = 0.4600 line-2-Via Pitch: 0.3500
[INFO GRT-0088] Layer met3 Track-Pitch = 0.6800 line-2-Via Pitch: 0.6150
[INFO GRT-0088] Layer met4 Track-Pitch = 0.9200 line-2-Via Pitch: 1.0400
[INFO GRT-0088] Layer met5 Track-Pitch = 3.4000 line-2-Via Pitch: 3.1100
[INFO GRT-0003] Macros: 0
[INFO GRT-0004] Blockages: 374499
[INFO GRT-0019] Found 125 clock nets.
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 23267
[INFO GRT-0017] Processing 1080663 blockages on layer met1.
[INFO GRT-0017] Processing 352 blockages on layer met4.
[INFO GRT-0017] Processing 306 blockages on layer met5.

[INFO GRT-0053] Routing resources analysis:
Routing Original Derated Resource
Layer Direction Resources Resources Reduction (%)
---------------------------------------------------------------
li1 Vertical 0 0 0.00%
met1 Horizontal 10045020 5144846 48.78%
met2 Vertical 7533765 4522140 39.98%
met3 Horizontal 5022510 3018528 39.90%
met4 Vertical 3013506 1510488 49.88%
met5 Horizontal 1004502 502336 49.99%
---------------------------------------------------------------

[INFO GRT-0104] Minimal overflow 288 occurring at round 0.
[INFO GRT-0111] Final number of vias: 371714
[INFO GRT-0112] Final usage 3D: 1764261
[WARNING GRT-0115] Global routing finished with overflow.

[INFO GRT-0096] Final congestion report:
Layer Resource Demand Usage (%) Max H / Max V / Total Overflow
---------------------------------------------------------------------------------------
li1 0 1 0.00% 0 / 1 / 1
met1 5144846 265565 5.16% 0 / 0 / 0
met2 4522140 265654 5.87% 0 / 5 / 248
met3 3018528 82049 2.72% 0 / 0 / 0
met4 1510488 35618 2.36% 0 / 2 / 39
met5 502336 232 0.05% 0 / 0 / 0
---------------------------------------------------------------------------------------
Total 14698338 649119 4.42% 0 / 8 / 288

[INFO GRT-0018] Total wirelength: 6003441 um
[INFO GPL-0036] TileLxLy: 0 0
[INFO GPL-0037] TileSize: 6900 6900
[INFO GPL-0038] TileCnt: 753 668
[INFO GPL-0039] numRoutingLayers: 6
[INFO GPL-0040] NumTiles: 503004
[INFO GPL-0063] TotalRouteOverflowH2: 0.0
[INFO GPL-0064] TotalRouteOverflowV2: 23.033336758613586
[INFO GPL-0065] OverflowTileCnt2: 183
[INFO GPL-0066] 0.5%RC: 0.9902508832851935
[INFO GPL-0067] 1.0%RC: 0.9400452604500419
[INFO GPL-0068] 2.0%RC: 0.8806628747663301
[INFO GPL-0069] 5.0%RC: 0.7686673171967613
[INFO GPL-0070] 0.5rcK: 1.0
[INFO GPL-0071] 1.0rcK: 1.0
[INFO GPL-0072] 2.0rcK: 0.0
[INFO GPL-0073] 5.0rcK: 0.0
[INFO GPL-0074] FinalRC: 0.9651481
[NesterovSolve] Iter: 480 overflow: 0.188057 HPWL: 2283655958
[NesterovSolve] Iter: 490 overflow: 0.166138 HPWL: 2287301711
[NesterovSolve] Iter: 500 overflow: 0.145241 HPWL: 2292035555
[NesterovSolve] Iter: 510 overflow: 0.124918 HPWL: 2297700101
[NesterovSolve] Iter: 520 overflow: 0.108189 HPWL: 2294952442
[NesterovSolve] Finished with Overflow: 0.098696

==========================================================================
global place report_checks -path_delay min
--------------------------------------------------------------------------
Startpoint: externalResetVector[24] (input port clocked by clk)
Endpoint: _145481_ (removal check against rising-edge clock clk)
Path Group: **async_default**
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 0.00 1.00 v externalResetVector[24] (in)
2 0.30 externalResetVector[24] (net)
0.43 0.22 1.22 v _122290_/B (sky130_fd_sc_hd__nand2_1)
0.12 0.20 1.42 ^ _122290_/Y (sky130_fd_sc_hd__nand2_1)
1 0.00 _000062_ (net)
0.12 0.00 1.42 ^ _145481_/SET_B (sky130_fd_sc_hd__dfbbp_1)
1.42 data arrival time

0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _145481_/CLK (sky130_fd_sc_hd__dfbbp_1)
0.09 0.09 library removal time
0.09 data required time
-----------------------------------------------------------------------------
0.09 data required time
-1.42 data arrival time
-----------------------------------------------------------------------------
1.32 slack (MET)


Startpoint: _144888_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _122419_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _144888_/CLK (sky130_fd_sc_hd__dfxtp_1)
0.06 0.30 0.30 ^ _144888_/Q (sky130_fd_sc_hd__dfxtp_1)
2 0.00 dataCache_1_.io_mem_cmd_payload_data[0] (net)
0.06 0.00 0.30 ^ _122419_/D (sky130_fd_sc_hd__dfxtp_1)
0.30 data arrival time

0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _122419_/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.04 -0.04 library hold time
-0.04 data required time
-----------------------------------------------------------------------------
-0.04 data required time
-0.30 data arrival time
-----------------------------------------------------------------------------
0.34 slack (MET)



==========================================================================
global place report_checks -path_delay max
--------------------------------------------------------------------------
Startpoint: externalResetVector[12] (input port clocked by clk)
Endpoint: _145469_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 0.00 1.00 v externalResetVector[12] (in)
2 0.67 externalResetVector[12] (net)
2.07 1.04 2.04 v _122277_/B (sky130_fd_sc_hd__nand2_1)
0.33 0.48 2.52 ^ _122277_/Y (sky130_fd_sc_hd__nand2_1)
1 0.00 _000038_ (net)
0.33 0.00 2.52 ^ _145469_/SET_B (sky130_fd_sc_hd__dfbbp_1)
2.52 data arrival time

0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ _145469_/CLK (sky130_fd_sc_hd__dfbbp_1)
-0.04 9.96 library recovery time
9.96 data required time
-----------------------------------------------------------------------------
9.96 data required time
-2.52 data arrival time
-----------------------------------------------------------------------------
7.44 slack (MET)


Startpoint: _143572_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _135902_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _143572_/CLK (sky130_fd_sc_hd__dfxtp_1)
0.23 0.42 0.42 ^ _143572_/Q (sky130_fd_sc_hd__dfxtp_1)
5 0.02 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] (net)
0.23 0.00 0.42 ^ _061278_/B (sky130_fd_sc_hd__xor2_1)
0.44 0.41 0.83 ^ _061278_/X (sky130_fd_sc_hd__xor2_1)
1 0.02 _025141_ (net)
0.44 0.00 0.84 ^ _061280_/B (sky130_fd_sc_hd__nor3_1)
0.22 0.28 1.12 v _061280_/Y (sky130_fd_sc_hd__nor3_1)
4 0.04 _025143_ (net)
0.22 0.00 1.12 v _061286_/A (sky130_fd_sc_hd__and2_0)
0.14 0.29 1.41 v _061286_/X (sky130_fd_sc_hd__and2_0)
4 0.02 _025149_ (net)
0.14 0.00 1.41 v _077118_/A1 (sky130_fd_sc_hd__a21oi_2)
18.63 13.41 14.82 ^ _077118_/Y (sky130_fd_sc_hd__a21oi_2)
117 1.63 _029150_ (net)
18.63 0.18 15.00 ^ _079640_/A1 (sky130_fd_sc_hd__o21a_1)
305.83 220.53 235.53 ^ _079640_/X (sky130_fd_sc_hd__o21a_1)
5371 35.58 _029825_ (net)
306.11 7.98 243.51 ^ _079726_/B (sky130_fd_sc_hd__nor2_1)
965.31 2851.46 3094.98 v _079726_/Y (sky130_fd_sc_hd__nor2_1)
363 3.64 _029911_ (net)
965.31 0.18 3095.15 v _108782_/A1 (sky130_fd_sc_hd__a32oi_1)
121.72 289.01 3384.17 ^ _108782_/Y (sky130_fd_sc_hd__a32oi_1)
1 0.01 _058946_ (net)
121.72 0.00 3384.17 ^ _108786_/A3 (sky130_fd_sc_hd__a31oi_1)
19.44 23.93 3408.09 v _108786_/Y (sky130_fd_sc_hd__a31oi_1)
1 0.05 _058950_ (net)
19.44 0.01 3408.10 v _108787_/A2 (sky130_fd_sc_hd__o21ai_0)
3.23 5.20 3413.31 ^ _108787_/Y (sky130_fd_sc_hd__o21ai_0)
1 0.00 _058951_ (net)
3.23 0.00 3413.31 ^ _108788_/D (sky130_fd_sc_hd__nor4_1)
1.88 1.85 3415.16 v _108788_/Y (sky130_fd_sc_hd__nor4_1)
1 0.11 _058952_ (net)
1.88 0.04 3415.19 v _108789_/B1 (sky130_fd_sc_hd__a211oi_1)
1.50 1.86 3417.05 ^ _108789_/Y (sky130_fd_sc_hd__a211oi_1)
1 0.05 _058953_ (net)
1.50 0.01 3417.06 ^ _109710_/A2 (sky130_fd_sc_hd__a31o_1)
0.07 0.26 3417.32 ^ _109710_/X (sky130_fd_sc_hd__a31o_1)
1 0.00 _013496_ (net)
0.07 0.00 3417.32 ^ _135902_/D (sky130_fd_sc_hd__dfxtp_1)
3417.32 data arrival time

0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ _135902_/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.07 9.93 library setup time
9.93 data required time
-----------------------------------------------------------------------------
9.93 data required time
-3417.32 data arrival time
-----------------------------------------------------------------------------
-3407.39 slack (VIOLATED)



==========================================================================
global place report_checks -unconstrained
--------------------------------------------------------------------------
Startpoint: externalResetVector[12] (input port clocked by clk)
Endpoint: _145469_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 0.00 1.00 v externalResetVector[12] (in)
2 0.67 externalResetVector[12] (net)
2.07 1.04 2.04 v _122277_/B (sky130_fd_sc_hd__nand2_1)
0.33 0.48 2.52 ^ _122277_/Y (sky130_fd_sc_hd__nand2_1)
1 0.00 _000038_ (net)
0.33 0.00 2.52 ^ _145469_/SET_B (sky130_fd_sc_hd__dfbbp_1)
2.52 data arrival time

0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ _145469_/CLK (sky130_fd_sc_hd__dfbbp_1)
-0.04 9.96 library recovery time
9.96 data required time
-----------------------------------------------------------------------------
9.96 data required time
-2.52 data arrival time
-----------------------------------------------------------------------------
7.44 slack (MET)


Startpoint: _143572_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _135902_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _143572_/CLK (sky130_fd_sc_hd__dfxtp_1)
0.23 0.42 0.42 ^ _143572_/Q (sky130_fd_sc_hd__dfxtp_1)
5 0.02 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] (net)
0.23 0.00 0.42 ^ _061278_/B (sky130_fd_sc_hd__xor2_1)
0.44 0.41 0.83 ^ _061278_/X (sky130_fd_sc_hd__xor2_1)
1 0.02 _025141_ (net)
0.44 0.00 0.84 ^ _061280_/B (sky130_fd_sc_hd__nor3_1)
0.22 0.28 1.12 v _061280_/Y (sky130_fd_sc_hd__nor3_1)
4 0.04 _025143_ (net)
0.22 0.00 1.12 v _061286_/A (sky130_fd_sc_hd__and2_0)
0.14 0.29 1.41 v _061286_/X (sky130_fd_sc_hd__and2_0)
4 0.02 _025149_ (net)
0.14 0.00 1.41 v _077118_/A1 (sky130_fd_sc_hd__a21oi_2)
18.63 13.41 14.82 ^ _077118_/Y (sky130_fd_sc_hd__a21oi_2)
117 1.63 _029150_ (net)
18.63 0.18 15.00 ^ _079640_/A1 (sky130_fd_sc_hd__o21a_1)
305.83 220.53 235.53 ^ _079640_/X (sky130_fd_sc_hd__o21a_1)
5371 35.58 _029825_ (net)
306.11 7.98 243.51 ^ _079726_/B (sky130_fd_sc_hd__nor2_1)
965.31 2851.46 3094.98 v _079726_/Y (sky130_fd_sc_hd__nor2_1)
363 3.64 _029911_ (net)
965.31 0.18 3095.15 v _108782_/A1 (sky130_fd_sc_hd__a32oi_1)
121.72 289.01 3384.17 ^ _108782_/Y (sky130_fd_sc_hd__a32oi_1)
1 0.01 _058946_ (net)
121.72 0.00 3384.17 ^ _108786_/A3 (sky130_fd_sc_hd__a31oi_1)
19.44 23.93 3408.09 v _108786_/Y (sky130_fd_sc_hd__a31oi_1)
1 0.05 _058950_ (net)
19.44 0.01 3408.10 v _108787_/A2 (sky130_fd_sc_hd__o21ai_0)
3.23 5.20 3413.31 ^ _108787_/Y (sky130_fd_sc_hd__o21ai_0)
1 0.00 _058951_ (net)
3.23 0.00 3413.31 ^ _108788_/D (sky130_fd_sc_hd__nor4_1)
1.88 1.85 3415.16 v _108788_/Y (sky130_fd_sc_hd__nor4_1)
1 0.11 _058952_ (net)
1.88 0.04 3415.19 v _108789_/B1 (sky130_fd_sc_hd__a211oi_1)
1.50 1.86 3417.05 ^ _108789_/Y (sky130_fd_sc_hd__a211oi_1)
1 0.05 _058953_ (net)
1.50 0.01 3417.06 ^ _109710_/A2 (sky130_fd_sc_hd__a31o_1)
0.07 0.26 3417.32 ^ _109710_/X (sky130_fd_sc_hd__a31o_1)
1 0.00 _013496_ (net)
0.07 0.00 3417.32 ^ _135902_/D (sky130_fd_sc_hd__dfxtp_1)
3417.32 data arrival time

0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ _135902_/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.07 9.93 library setup time
9.93 data required time
-----------------------------------------------------------------------------
9.93 data required time
-3417.32 data arrival time
-----------------------------------------------------------------------------
-3407.39 slack (VIOLATED)



==========================================================================
global place report_tns
--------------------------------------------------------------------------
tns -721128.38

==========================================================================
global place report_wns
--------------------------------------------------------------------------
wns -3407.39

==========================================================================
global place report_worst_slack
--------------------------------------------------------------------------
worst slack -3407.39

==========================================================================
global place report_clock_skew
--------------------------------------------------------------------------
Clock clk
Latency CRPR Skew
_145458_/CLK ^
0.00
_143514_/CLK ^
0.00 0.00 0.00


==========================================================================
global place report_power
--------------------------------------------------------------------------
Group Internal Switching Leakage Total
Power Power Power Power
----------------------------------------------------------------
Sequential 1.00e-01 5.36e-03 2.04e-07 1.06e-01 39.0%
Combinational 1.48e-01 1.69e-02 1.65e-07 1.65e-01 61.0%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 2.49e-01 2.22e-02 3.69e-07 2.71e-01 100.0%
91.8% 8.2% 0.0%

==========================================================================
global place report_design_area
--------------------------------------------------------------------------
Design area 1274500 u^2 6% utilization.

Elapsed time: 2:55.77[h:]min:sec. CPU time: user 174.41 sys 1.27 (99%). Peak memory: 2498404KB.

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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/3_1_place_gp.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 344463 components and 975384 component-terminals.
[INFO ODB-0132] Created 2 special nets and 688926 connections.
[INFO ODB-0133] Created 77777 nets and 286452 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/3_1_place_gp.def
Found 0 macro blocks.
Using 1u default distance from corners.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0010] Tentative 0 to set up sections.
[INFO PPL-0001] Number of slots 18082
[INFO PPL-0002] Number of I/O 254
[INFO PPL-0003] Number of I/O w/sink 254
[INFO PPL-0004] Number of I/O w/o sink 72
[INFO PPL-0005] Slots per section 200
[INFO PPL-0006] Slots increase factor 0.01
[INFO PPL-0008] Successfully assigned pins to sections.
[INFO PPL-0012] I/O nets HPWL: 231177.19 um.
Elapsed time: 0:05.34[h:]min:sec. CPU time: user 5.05 sys 0.25 (99%). Peak memory: 1192196KB.

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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/4_1_cts.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 349723 components and 996424 component-terminals.
[INFO ODB-0132] Created 2 special nets and 699446 connections.
[INFO ODB-0133] Created 83037 nets and 296650 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/4_1_cts.def
[INFO DPL-0001] Placed 2328695 filler instances.
Elapsed time: 0:15.56[h:]min:sec. CPU time: user 14.85 sys 0.67 (99%). Peak memory: 2321232KB.

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{
"drt::wire length::total" : 4809559
, "drt::vias::total" : 677660
}

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[INFO] Reporting cells prior to loading DEF ...
[INFO] Reading DEF ...
[INFO] Clearing cells...
[INFO] ... preserving 'VIA_L1M1_PR'
[INFO] ... preserving 'VIA_L1M1_PR_R'
[INFO] ... preserving 'VIA_L1M1_PR_M'
[INFO] ... preserving 'VIA_L1M1_PR_MR'
[INFO] ... preserving 'VIA_L1M1_PR_C'
[INFO] ... preserving 'VIA_M1M2_PR'
[INFO] ... preserving 'VIA_M1M2_PR_R'
[INFO] ... preserving 'VIA_M1M2_PR_M'
[INFO] ... preserving 'VIA_M1M2_PR_MR'
[INFO] ... preserving 'VIA_M1M2_PR_C'
[INFO] ... preserving 'VIA_M2M3_PR'
[INFO] ... preserving 'VIA_M2M3_PR_R'
[INFO] ... preserving 'VIA_M2M3_PR_M'
[INFO] ... preserving 'VIA_M2M3_PR_MR'
[INFO] ... preserving 'VIA_M2M3_PR_C'
[INFO] ... preserving 'VIA_M3M4_PR'
[INFO] ... preserving 'VIA_M3M4_PR_R'
[INFO] ... preserving 'VIA_M3M4_PR_M'
[INFO] ... preserving 'VIA_M3M4_PR_MR'
[INFO] ... preserving 'VIA_M3M4_PR_C'
[INFO] ... preserving 'VIA_M4M5_PR'
[INFO] ... preserving 'VIA_M4M5_PR_R'
[INFO] ... preserving 'VIA_M4M5_PR_M'
[INFO] ... preserving 'VIA_M4M5_PR_MR'
[INFO] ... preserving 'VIA_M4M5_PR_C'
[INFO] ... preserving 'VIA_via_1600x480'
[INFO] ... preserving 'VIA_via2_1600x480'
[INFO] ... preserving 'VIA_via3_1600x480'
[INFO] ... preserving 'VIA_via4_1600x1600'
[INFO] Merging GDS/OAS files...
./platforms/sky130hd/gds/sky130_fd_sc_hd.gds
[INFO] Copying toplevel cell 'A2P_WB'
INFO: Reading config file: ./platforms/sky130hd/fill.json
[INFO] Checking for missing cell from GDS/OAS...
[INFO] All LEF cells have matching GDS/OAS cells
[INFO] Checking for orphan cell in the final layout...
[INFO] No orphan cells
[INFO] Writing out GDS/OAS 'results/sky130hd/a2p/base/6_1_merged.gds'
Elapsed time: 0:33.23[h:]min:sec. CPU time: user 31.21 sys 2.00 (99%). Peak memory: 5201532KB.

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{
}

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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[WTF] clk_period=10.0
number instances in verilog is 419899
[INFO IFP-0001] Added 1535 rows of 10390 sites.
[INFO RSZ-0026] Removed 33874 buffers.
Default units for flow
time 1ns
capacitance 1pF
resistance 1kohm
voltage 1v
current 1mA
power 1nW
distance 1um

==========================================================================
floorplan final report_checks -path_delay min
--------------------------------------------------------------------------
Startpoint: externalResetVector[1] (input port clocked by clk)
Endpoint: _392865_ (removal check against rising-edge clock clk)
Path Group: **async_default**
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 0.00 v externalResetVector[1] (in)
2 0.00 externalResetVector[1] (net)
0.00 0.00 0.00 v _334882_/B (sky130_fd_sc_hd__nand2_1)
0.05 0.05 0.05 ^ _334882_/Y (sky130_fd_sc_hd__nand2_1)
1 0.00 _000305_ (net)
0.05 0.01 0.06 ^ _392865_/SET_B (sky130_fd_sc_hd__dfbbp_1)
0.06 data arrival time

0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _392865_/CLK (sky130_fd_sc_hd__dfbbp_1)
0.11 0.11 library removal time
0.11 data required time
-----------------------------------------------------------------------------
0.11 data required time
-0.06 data arrival time
-----------------------------------------------------------------------------
-0.05 slack (VIOLATED)


Startpoint: iBusWB_DAT_MISO[0] (input port clocked by clk)
Endpoint: _336820_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 0.00 ^ iBusWB_DAT_MISO[0] (in)
1 0.00 iBusWB_DAT_MISO[0] (net)
0.00 0.00 0.00 ^ _336820_/D (sky130_fd_sc_hd__dfxtp_1)
0.00 data arrival time

0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _336820_/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.03 -0.03 library hold time
-0.03 data required time
-----------------------------------------------------------------------------
-0.03 data required time
-0.00 data arrival time
-----------------------------------------------------------------------------
0.03 slack (MET)



==========================================================================
floorplan final report_checks -path_delay max
--------------------------------------------------------------------------
Startpoint: externalResetVector[1] (input port clocked by clk)
Endpoint: _392865_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 0.00 ^ externalResetVector[1] (in)
2 0.00 externalResetVector[1] (net)
0.00 0.00 0.00 ^ _334847_/A_N (sky130_fd_sc_hd__nand2b_1)
0.04 0.07 0.07 ^ _334847_/Y (sky130_fd_sc_hd__nand2b_1)
1 0.00 _000304_ (net)
0.04 0.00 0.07 ^ _392865_/RESET_B (sky130_fd_sc_hd__dfbbp_1)
0.07 data arrival time

0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ _392865_/CLK (sky130_fd_sc_hd__dfbbp_1)
-0.07 9.93 library recovery time
9.93 data required time
-----------------------------------------------------------------------------
9.93 data required time
-0.07 data arrival time
-----------------------------------------------------------------------------
9.85 slack (MET)


Startpoint: _347929_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG
(rising clock gating-check end-point clocked by clk')
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _347929_/CLK (sky130_fd_sc_hd__dfxtp_1)
1.60 1.38 1.38 ^ _347929_/Q (sky130_fd_sc_hd__dfxtp_1)
43 0.17 dataCache_1_.stageB_mmuRsp_isIoAccess (net)
1.60 0.00 1.38 ^ _170832_/A (sky130_fd_sc_hd__nor2b_1)
0.29 0.25 1.64 v _170832_/Y (sky130_fd_sc_hd__nor2b_1)
5 0.01 _057084_ (net)
0.29 0.00 1.64 v _170981_/B1 (sky130_fd_sc_hd__a21oi_1)
0.17 0.21 1.85 ^ _170981_/Y (sky130_fd_sc_hd__a21oi_1)
1 0.00 _057164_ (net)
0.17 0.00 1.85 ^ _170982_/B (sky130_fd_sc_hd__nor2_1)
0.05 0.07 1.92 v _170982_/Y (sky130_fd_sc_hd__nor2_1)
2 0.00 _057165_ (net)
0.05 0.00 1.92 v _170984_/A3 (sky130_fd_sc_hd__o31a_1)
3.37 2.89 4.81 v _170984_/X (sky130_fd_sc_hd__o31a_1)
363 0.84 _057167_ (net)
3.37 0.00 4.82 v _171012_/A1 (sky130_fd_sc_hd__a21oi_1)
1.55 2.46 7.27 ^ _171012_/Y (sky130_fd_sc_hd__a21oi_1)
31 0.08 _057195_ (net)
1.55 0.00 7.28 ^ _174406_/A (sky130_fd_sc_hd__nand2_1)
0.39 0.39 7.67 v _174406_/Y (sky130_fd_sc_hd__nand2_1)
8 0.02 _059918_ (net)
0.39 0.00 7.67 v _174579_/B1 (sky130_fd_sc_hd__o2bb2ai_1)
894.69 658.29 665.96 ^ _174579_/Y (sky130_fd_sc_hd__o2bb2ai_1)
13060 47.78 _060082_ (net)
894.69 0.00 665.96 ^ _174590_/A2 (sky130_fd_sc_hd__o21ai_0)
21.06 5385.83 6051.78 v _174590_/Y (sky130_fd_sc_hd__o21ai_0)
1024 1.99 IBusCachedPlugin_cache.ways_0_datas.adr[0] (net)
21.06 0.00 6051.79 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/C (sky130_fd_sc_hd__and4b_2)
0.68 7.89 6059.68 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/X (sky130_fd_sc_hd__and4b_2)
8 0.02 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.SEL0 (net)
0.68 0.00 6059.68 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/A (sky130_fd_sc_hd__and2_1)
0.20 0.36 6060.04 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/X (sky130_fd_sc_hd__and2_1)
1 0.00 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.WE0_WIRE (net)
0.20 0.00 6060.04 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/GATE (sky130_fd_sc_hd__dlclkp_1)
6060.04 data arrival time

0.00 5.00 5.00 clock clk' (rise edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 clock reconvergence pessimism
5.00 ^ IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/CLK (sky130_fd_sc_hd__dlclkp_1)
-0.19 4.81 library setup time
4.81 data required time
-----------------------------------------------------------------------------
4.81 data required time
-6060.04 data arrival time
-----------------------------------------------------------------------------
-6055.23 slack (VIOLATED)



==========================================================================
floorplan final report_checks -unconstrained
--------------------------------------------------------------------------
Startpoint: externalResetVector[1] (input port clocked by clk)
Endpoint: _392865_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 0.00 ^ externalResetVector[1] (in)
2 0.00 externalResetVector[1] (net)
0.00 0.00 0.00 ^ _334847_/A_N (sky130_fd_sc_hd__nand2b_1)
0.04 0.07 0.07 ^ _334847_/Y (sky130_fd_sc_hd__nand2b_1)
1 0.00 _000304_ (net)
0.04 0.00 0.07 ^ _392865_/RESET_B (sky130_fd_sc_hd__dfbbp_1)
0.07 data arrival time

0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ _392865_/CLK (sky130_fd_sc_hd__dfbbp_1)
-0.07 9.93 library recovery time
9.93 data required time
-----------------------------------------------------------------------------
9.93 data required time
-0.07 data arrival time
-----------------------------------------------------------------------------
9.85 slack (MET)


Startpoint: _347929_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG
(rising clock gating-check end-point clocked by clk')
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _347929_/CLK (sky130_fd_sc_hd__dfxtp_1)
1.60 1.38 1.38 ^ _347929_/Q (sky130_fd_sc_hd__dfxtp_1)
43 0.17 dataCache_1_.stageB_mmuRsp_isIoAccess (net)
1.60 0.00 1.38 ^ _170832_/A (sky130_fd_sc_hd__nor2b_1)
0.29 0.25 1.64 v _170832_/Y (sky130_fd_sc_hd__nor2b_1)
5 0.01 _057084_ (net)
0.29 0.00 1.64 v _170981_/B1 (sky130_fd_sc_hd__a21oi_1)
0.17 0.21 1.85 ^ _170981_/Y (sky130_fd_sc_hd__a21oi_1)
1 0.00 _057164_ (net)
0.17 0.00 1.85 ^ _170982_/B (sky130_fd_sc_hd__nor2_1)
0.05 0.07 1.92 v _170982_/Y (sky130_fd_sc_hd__nor2_1)
2 0.00 _057165_ (net)
0.05 0.00 1.92 v _170984_/A3 (sky130_fd_sc_hd__o31a_1)
3.37 2.89 4.81 v _170984_/X (sky130_fd_sc_hd__o31a_1)
363 0.84 _057167_ (net)
3.37 0.00 4.82 v _171012_/A1 (sky130_fd_sc_hd__a21oi_1)
1.55 2.46 7.27 ^ _171012_/Y (sky130_fd_sc_hd__a21oi_1)
31 0.08 _057195_ (net)
1.55 0.00 7.28 ^ _174406_/A (sky130_fd_sc_hd__nand2_1)
0.39 0.39 7.67 v _174406_/Y (sky130_fd_sc_hd__nand2_1)
8 0.02 _059918_ (net)
0.39 0.00 7.67 v _174579_/B1 (sky130_fd_sc_hd__o2bb2ai_1)
894.69 658.29 665.96 ^ _174579_/Y (sky130_fd_sc_hd__o2bb2ai_1)
13060 47.78 _060082_ (net)
894.69 0.00 665.96 ^ _174590_/A2 (sky130_fd_sc_hd__o21ai_0)
21.06 5385.83 6051.78 v _174590_/Y (sky130_fd_sc_hd__o21ai_0)
1024 1.99 IBusCachedPlugin_cache.ways_0_datas.adr[0] (net)
21.06 0.00 6051.79 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/C (sky130_fd_sc_hd__and4b_2)
0.68 7.89 6059.68 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND3/X (sky130_fd_sc_hd__and4b_2)
8 0.02 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.SEL0 (net)
0.68 0.00 6059.68 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/A (sky130_fd_sc_hd__and2_1)
0.20 0.36 6060.04 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND/X (sky130_fd_sc_hd__and2_1)
1 0.00 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.WE0_WIRE (net)
0.20 0.00 6060.04 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/GATE (sky130_fd_sc_hd__dlclkp_1)
6060.04 data arrival time

0.00 5.00 5.00 clock clk' (rise edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 clock reconvergence pessimism
5.00 ^ IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/CLK (sky130_fd_sc_hd__dlclkp_1)
-0.19 4.81 library setup time
4.81 data required time
-----------------------------------------------------------------------------
4.81 data required time
-6060.04 data arrival time
-----------------------------------------------------------------------------
-6055.23 slack (VIOLATED)



==========================================================================
floorplan final report_tns
--------------------------------------------------------------------------
tns -14775986.00

==========================================================================
floorplan final report_wns
--------------------------------------------------------------------------
wns -6055.23

==========================================================================
floorplan final report_worst_slack
--------------------------------------------------------------------------
worst slack -6055.23

==========================================================================
floorplan final report_clock_skew
--------------------------------------------------------------------------
Clock clk
Latency CRPR Skew
IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[0].genblk1.STORAGE/GATE ^
0.26
IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.Do0_FF[0]/CLK ^
0.00 0.00 0.26


==========================================================================
floorplan final report_power
--------------------------------------------------------------------------
Group Internal Switching Leakage Total
Power Power Power Power
----------------------------------------------------------------
Sequential 3.98e-01 1.16e-02 9.12e-07 4.09e-01 18.1%
Combinational 1.75e+00 9.21e-02 8.63e-07 1.84e+00 81.6%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 2.15e+00 1.04e-01 1.77e-06 2.26e+00 100.0%
95.4% 4.6% 0.0%

==========================================================================
floorplan final report_design_area
--------------------------------------------------------------------------
Design area 4541698 u^2 23% utilization.

Elapsed time: 2:35.18[h:]min:sec. CPU time: user 154.64 sys 0.51 (99%). Peak memory: 1373324KB.

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build/openroad/logs/clk_100_allrams/2_2_floorplan_io.json
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{
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build/openroad/logs/clk_100_allrams/2_2_floorplan_io.log
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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_1_floorplan.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 386025 components and 2056090 component-terminals.
[INFO ODB-0133] Created 317870 nets and 1283758 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_1_floorplan.def
Found 0 macro blocks.
Using 1u default distance from corners.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0007] Random pin placement.
Elapsed time: 0:05.63[h:]min:sec. CPU time: user 5.35 sys 0.23 (99%). Peak memory: 576964KB.

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build/openroad/logs/clk_100_allrams/2_3_tdms.json
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build/openroad/logs/clk_100_allrams/2_3_tdms_place.log
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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_2_floorplan_io.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 386025 components and 2056090 component-terminals.
[INFO ODB-0133] Created 317870 nets and 1283758 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_2_floorplan_io.def
[WTF] clk_period=10.0
No macros found: Skipping global_placement
Elapsed time: 0:05.69[h:]min:sec. CPU time: user 5.43 sys 0.23 (99%). Peak memory: 562896KB.

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build/openroad/logs/clk_100_allrams/2_4_mplace.json
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build/openroad/logs/clk_100_allrams/2_4_mplace.log
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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_3_floorplan_tdms.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 386025 components and 2056090 component-terminals.
[INFO ODB-0133] Created 317870 nets and 1283758 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_3_floorplan_tdms.def
[WTF] clk_period=10.0
No macros found: Skipping macro_placement
Elapsed time: 0:05.72[h:]min:sec. CPU time: user 5.47 sys 0.21 (99%). Peak memory: 561676KB.

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build/openroad/logs/clk_100_allrams/2_5_tapcell.json
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build/openroad/logs/clk_100_allrams/2_5_tapcell.log
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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_4_floorplan_macro.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 386025 components and 2056090 component-terminals.
[INFO ODB-0133] Created 317870 nets and 1283758 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_4_floorplan_macro.def
[WARNING TAP-0014] endcap_cpp option is deprecated.
[INFO TAP-0001] Found 0 macro blocks.
[INFO TAP-0002] Original rows: 1535
[INFO TAP-0003] Created 0 rows for a total of 1535 rows.
[INFO TAP-0005] Inserted 265901 tapcells.
Elapsed time: 0:05.79[h:]min:sec. CPU time: user 5.54 sys 0.22 (99%). Peak memory: 418888KB.

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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_5_floorplan_tapcell.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0094] Created 400000 Insts
[INFO ODB-0094] Created 500000 Insts
[INFO ODB-0094] Created 600000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 651926 components and 2587892 component-terminals.
[INFO ODB-0133] Created 317870 nets and 1283758 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_5_floorplan_tapcell.def
[INFO PDN-0016] Power Delivery Network Generator: Generating PDN
config: ./platforms/sky130hd/pdn.cfg
[INFO PDN-0008] Design name is A2P_WB.
[INFO PDN-0009] Reading technology data.
[INFO PDN-0011] ****** INFO ******
Type: stdcell, grid
Stdcell Rails
Layer: met1 - width: 0.480 pitch: 5.440 offset: 0.000
Straps
Layer: met4 - width: 1.600 pitch: 27.140 offset: 13.570
Layer: met5 - width: 1.600 pitch: 27.200 offset: 13.600
Connect: {met1 met4} {met4 met5}
Type: macro, CORE_macro_grid_1
Macro orientation: R0 R180 MX MY
Connect: {met4_PIN_ver met5}
Type: macro, CORE_macro_grid_2
Macro orientation: R90 R270 MXR90 MYR90
Connect: {met4_PIN_hor met5}
[INFO PDN-0012] **** END INFO ****
[INFO PDN-0013] Inserting stdcell grid - grid.
[INFO PDN-0015] Writing to database.
Elapsed time: 0:45.08[h:]min:sec. CPU time: user 43.84 sys 1.19 (99%). Peak memory: 3748060KB.

2
build/openroad/logs/clk_100_allrams/3_1_place_gp.json
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{
}

485
build/openroad/logs/clk_100_allrams/3_1_place_gp.log
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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/2_floorplan.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0094] Created 400000 Insts
[INFO ODB-0094] Created 500000 Insts
[INFO ODB-0094] Created 600000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 651926 components and 2587892 component-terminals.
[INFO ODB-0132] Created 2 special nets and 1303852 connections.
[INFO ODB-0133] Created 317870 nets and 1283758 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/2_floorplan.def
[INFO GPL-0002] DBU: 1000
[INFO GPL-0003] SiteSize: 460 2720
[INFO GPL-0004] CoreAreaLxLy: 210220 212160
[INFO GPL-0005] CoreAreaUxUy: 4989620 4387360
[INFO GPL-0006] NumInstances: 651926
[INFO GPL-0007] NumPlaceInstances: 386025
[INFO GPL-0008] NumFixedInstances: 265901
[INFO GPL-0009] NumDummyInstances: 0
[INFO GPL-0010] NumNets: 317870
[INFO GPL-0011] NumPins: 1284012
[INFO GPL-0012] DieAreaLxLy: 0 0
[INFO GPL-0013] DieAreaUxUy: 5200000 4609140
[INFO GPL-0014] CoreAreaLxLy: 210220 212160
[INFO GPL-0015] CoreAreaUxUy: 4989620 4387360
[INFO GPL-0016] CoreArea: 19954950880000
[INFO GPL-0017] NonPlaceInstsArea: 332695331200
[INFO GPL-0018] PlaceInstsArea: 8405654188800
[INFO GPL-0019] Util(%): 42.84
[INFO GPL-0020] StdInstsArea: 8405654188800
[INFO GPL-0021] MacroInstsArea: 0
[InitialPlace] Iter: 1 CG Error: 0.00415516 HPWL: 3867717600
[InitialPlace] Iter: 2 CG Error: 0.00007246 HPWL: 3863367077
[InitialPlace] Iter: 3 CG Error: 0.00001159 HPWL: 3883391444
[InitialPlace] Iter: 4 CG Error: 0.00001345 HPWL: 3891885687
[InitialPlace] Iter: 5 CG Error: 0.00001456 HPWL: 3889521585
[InitialPlace] Iter: 6 CG Error: 0.00000666 HPWL: 3888913848
[INFO GPL-0031] FillerInit: NumGCells: 541159
[INFO GPL-0032] FillerInit: NumGNets: 317870
[INFO GPL-0033] FillerInit: NumGPins: 1284012
[INFO GPL-0023] TargetDensity: 0.60
[INFO GPL-0024] AveragePlaceInstArea: 21774895
[INFO GPL-0025] IdealBinArea: 36291492
[INFO GPL-0026] IdealBinCnt: 549852
[INFO GPL-0027] TotalBinArea: 19954950880000
[INFO GPL-0028] BinCnt: 512 512
[INFO GPL-0029] BinSize: 9335 8155
[INFO GPL-0030] NumBins: 262144
[NesterovSolve] Iter: 1 overflow: 0.998845 HPWL: 1180500025
[NesterovSolve] Iter: 10 overflow: 0.996763 HPWL: 1383805105
[NesterovSolve] Iter: 20 overflow: 0.995224 HPWL: 1474291212
[NesterovSolve] Iter: 30 overflow: 0.994488 HPWL: 1533722689
[NesterovSolve] Iter: 40 overflow: 0.994295 HPWL: 1546586218
[NesterovSolve] Iter: 50 overflow: 0.994281 HPWL: 1546146528
[NesterovSolve] Iter: 60 overflow: 0.99432 HPWL: 1535568772
[NesterovSolve] Iter: 70 overflow: 0.994345 HPWL: 1530188704
[NesterovSolve] Iter: 80 overflow: 0.994262 HPWL: 1533229326
[NesterovSolve] Iter: 90 overflow: 0.99423 HPWL: 1537638589
[NesterovSolve] Iter: 100 overflow: 0.994137 HPWL: 1539012361
[NesterovSolve] Iter: 110 overflow: 0.994094 HPWL: 1539541437
[NesterovSolve] Iter: 120 overflow: 0.994015 HPWL: 1541128962
[NesterovSolve] Iter: 130 overflow: 0.993987 HPWL: 1545100411
[NesterovSolve] Iter: 140 overflow: 0.993947 HPWL: 1551408823
[NesterovSolve] Iter: 150 overflow: 0.993883 HPWL: 1560006569
[NesterovSolve] Iter: 160 overflow: 0.993816 HPWL: 1573137353
[NesterovSolve] Iter: 170 overflow: 0.993782 HPWL: 1593520684
[NesterovSolve] Iter: 180 overflow: 0.993706 HPWL: 1628314635
[NesterovSolve] Iter: 190 overflow: 0.993551 HPWL: 1683084197
[NesterovSolve] Iter: 200 overflow: 0.993304 HPWL: 1759538391
[NesterovSolve] Iter: 210 overflow: 0.992975 HPWL: 1857231666
[NesterovSolve] Iter: 220 overflow: 0.992348 HPWL: 1978689253
[NesterovSolve] Iter: 230 overflow: 0.991302 HPWL: 2125167500
[NesterovSolve] Iter: 240 overflow: 0.989686 HPWL: 2299610841
[NesterovSolve] Iter: 250 overflow: 0.987221 HPWL: 2513196172
[NesterovSolve] Iter: 260 overflow: 0.983451 HPWL: 2784510939
[NesterovSolve] Iter: 270 overflow: 0.978863 HPWL: 3141905617
[NesterovSolve] Iter: 280 overflow: 0.973151 HPWL: 3609119836
[NesterovSolve] Iter: 290 overflow: 0.965563 HPWL: 4185323792
[NesterovSolve] Iter: 300 overflow: 0.955086 HPWL: 4863482666
[NesterovSolve] Iter: 310 overflow: 0.942691 HPWL: 5624032958
[NesterovSolve] Iter: 320 overflow: 0.928545 HPWL: 6411407597
[NesterovSolve] Iter: 330 overflow: 0.912421 HPWL: 7159465127
[NesterovSolve] Iter: 340 overflow: 0.892405 HPWL: 7797782782
[NesterovSolve] Iter: 350 overflow: 0.866639 HPWL: 8329655506
[NesterovSolve] Iter: 360 overflow: 0.838202 HPWL: 8737315357
[NesterovSolve] Iter: 370 overflow: 0.807709 HPWL: 9228870381
[NesterovSolve] Iter: 380 overflow: 0.774372 HPWL: 9858444582
[NesterovSolve] Iter: 390 overflow: 0.74003 HPWL: 10506023896
[NesterovSolve] Iter: 400 overflow: 0.706632 HPWL: 11706861023
[NesterovSolve] Iter: 410 overflow: 0.667068 HPWL: 13542833928
[NesterovSolve] Iter: 420 overflow: 0.639148 HPWL: 13843488224
[NesterovSolve] Snapshot saved at iter = 427
[NesterovSolve] Iter: 430 overflow: 0.590578 HPWL: 14582617111
[NesterovSolve] Iter: 440 overflow: 0.554742 HPWL: 13331266378
[NesterovSolve] Iter: 450 overflow: 0.512624 HPWL: 12570495474
[NesterovSolve] Iter: 460 overflow: 0.476803 HPWL: 12043325892
[NesterovSolve] Iter: 470 overflow: 0.447001 HPWL: 11806171542
[NesterovSolve] Iter: 480 overflow: 0.415581 HPWL: 11257953580
[NesterovSolve] Iter: 490 overflow: 0.388441 HPWL: 10823311280
[NesterovSolve] Iter: 500 overflow: 0.360349 HPWL: 10409735593
[NesterovSolve] Iter: 510 overflow: 0.336177 HPWL: 10037738990
[NesterovSolve] Iter: 520 overflow: 0.315769 HPWL: 9716054384
[NesterovSolve] Iter: 530 overflow: 0.293944 HPWL: 9456435951
[NesterovSolve] Iter: 540 overflow: 0.266344 HPWL: 9268137881
[NesterovSolve] Iter: 550 overflow: 0.227483 HPWL: 9129070380
[INFO GPL-0075] Routability numCall: 1 inflationIterCnt: 1 bloatIterCnt: 0
[INFO GRT-0020] Min routing layer: met1
[INFO GRT-0021] Max routing layer: met5
[INFO GRT-0022] Global adjustment: 0%
[INFO GRT-0023] Grid origin: (0, 0)
[WARNING GRT-0043] No OR_DEFAULT vias defined.
[INFO GRT-0224] Chose via L1M1_PR as default.
[INFO GRT-0224] Chose via M1M2_PR as default.
[INFO GRT-0224] Chose via M2M3_PR as default.
[INFO GRT-0224] Chose via M3M4_PR as default.
[INFO GRT-0224] Chose via M4M5_PR as default.
[INFO GRT-0088] Layer li1 Track-Pitch = 0.4600 line-2-Via Pitch: 0.3400
[INFO GRT-0088] Layer met1 Track-Pitch = 0.3400 line-2-Via Pitch: 0.3400
[INFO GRT-0088] Layer met2 Track-Pitch = 0.4600 line-2-Via Pitch: 0.3500
[INFO GRT-0088] Layer met3 Track-Pitch = 0.6800 line-2-Via Pitch: 0.6150
[INFO GRT-0088] Layer met4 Track-Pitch = 0.9200 line-2-Via Pitch: 1.0400
[INFO GRT-0088] Layer met5 Track-Pitch = 3.4000 line-2-Via Pitch: 3.1100
[INFO GRT-0003] Macros: 0
[INFO GRT-0004] Blockages: 1977156
[INFO GRT-0019] Found 17533 clock nets.
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 67698
[INFO GRT-0017] Processing 3379039 blockages on layer met1.
[INFO GRT-0017] Processing 352 blockages on layer met4.
[INFO GRT-0017] Processing 306 blockages on layer met5.

[INFO GRT-0053] Routing resources analysis:
Routing Original Derated Resource
Layer Direction Resources Resources Reduction (%)
---------------------------------------------------------------
li1 Vertical 0 0 0.00%
met1 Horizontal 10045020 4937568 50.85%
met2 Vertical 7533765 4522140 39.98%
met3 Horizontal 5022510 3018528 39.90%
met4 Vertical 3013506 1510488 49.88%
met5 Horizontal 1004502 502336 49.99%
---------------------------------------------------------------

[INFO GRT-0104] Minimal overflow 965 occurring at round 0.
[INFO GRT-0111] Final number of vias: 1734719
[INFO GRT-0112] Final usage 3D: 8145910
[WARNING GRT-0115] Global routing finished with overflow.

[INFO GRT-0096] Final congestion report:
Layer Resource Demand Usage (%) Max H / Max V / Total Overflow
---------------------------------------------------------------------------------------
li1 0 39 0.00% 0 / 2 / 39
met1 4937568 1247337 25.26% 7 / 0 / 27
met2 4522140 1262928 27.93% 0 / 5 / 735
met3 3018528 272168 9.02% 2 / 0 / 2
met4 1510488 157552 10.43% 0 / 2 / 161
met5 502336 1729 0.34% 1 / 0 / 1
---------------------------------------------------------------------------------------
Total 14491060 2941753 20.30% 10 / 9 / 965

[INFO GRT-0018] Total wirelength: 27717341 um
[INFO GPL-0036] TileLxLy: 0 0
[INFO GPL-0037] TileSize: 6900 6900
[INFO GPL-0038] TileCnt: 753 668
[INFO GPL-0039] numRoutingLayers: 6
[INFO GPL-0040] NumTiles: 503004
[INFO GPL-0063] TotalRouteOverflowH2: 0.7999999523162842
[INFO GPL-0064] TotalRouteOverflowV2: 75.83334827423096
[INFO GPL-0065] OverflowTileCnt2: 661
[INFO GPL-0066] 0.5%RC: 1.015139418701184
[INFO GPL-0067] 1.0%RC: 1.0075704650368604
[INFO GPL-0068] 2.0%RC: 1.0012994584827064
[INFO GPL-0069] 5.0%RC: 0.9398297566571524
[INFO GPL-0070] 0.5rcK: 1.0
[INFO GPL-0071] 1.0rcK: 1.0
[INFO GPL-0072] 2.0rcK: 0.0
[INFO GPL-0073] 5.0rcK: 0.0
[INFO GPL-0074] FinalRC: 1.0113549
[NesterovSolve] Iter: 560 overflow: 0.192131 HPWL: 8951726949
[NesterovSolve] Iter: 570 overflow: 0.164959 HPWL: 8896051253
[NesterovSolve] Iter: 580 overflow: 0.142472 HPWL: 8828665026
[NesterovSolve] Iter: 590 overflow: 0.123891 HPWL: 8765586474
[NesterovSolve] Iter: 600 overflow: 0.1076 HPWL: 8764798375
[NesterovSolve] Finished with Overflow: 0.098959

==========================================================================
global place report_checks -path_delay min
--------------------------------------------------------------------------
Startpoint: externalResetVector[1] (input port clocked by clk)
Endpoint: _392865_ (removal check against rising-edge clock clk)
Path Group: **async_default**
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 0.00 v externalResetVector[1] (in)
2 0.21 externalResetVector[1] (net)
0.21 0.11 0.11 v _334882_/B (sky130_fd_sc_hd__nand2_1)
0.08 0.14 0.24 ^ _334882_/Y (sky130_fd_sc_hd__nand2_1)
1 0.00 _000305_ (net)
0.08 0.00 0.24 ^ _392865_/SET_B (sky130_fd_sc_hd__dfbbp_1)
0.24 data arrival time

0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _392865_/CLK (sky130_fd_sc_hd__dfbbp_1)
0.10 0.10 library removal time
0.10 data required time
-----------------------------------------------------------------------------
0.10 data required time
-0.24 data arrival time
-----------------------------------------------------------------------------
0.14 slack (MET)


Startpoint: iBusWB_DAT_MISO[29] (input port clocked by clk)
Endpoint: _336849_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 0.00 ^ iBusWB_DAT_MISO[29] (in)
1 0.03 iBusWB_DAT_MISO[29] (net)
0.01 0.00 0.00 ^ _336849_/D (sky130_fd_sc_hd__dfxtp_1)
0.00 data arrival time

0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _336849_/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.03 -0.03 library hold time
-0.03 data required time
-----------------------------------------------------------------------------
-0.03 data required time
-0.00 data arrival time
-----------------------------------------------------------------------------
0.03 slack (MET)



==========================================================================
global place report_checks -path_delay max
--------------------------------------------------------------------------
Startpoint: externalResetVector[21] (input port clocked by clk)
Endpoint: _392885_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 0.00 v externalResetVector[21] (in)
2 0.78 externalResetVector[21] (net)
2.83 1.41 1.41 v _334904_/B (sky130_fd_sc_hd__nand2_1)
0.48 0.60 2.01 ^ _334904_/Y (sky130_fd_sc_hd__nand2_1)
1 0.00 _000345_ (net)
0.48 0.00 2.01 ^ _392885_/SET_B (sky130_fd_sc_hd__dfbbp_1)
2.01 data arrival time

0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ _392885_/CLK (sky130_fd_sc_hd__dfbbp_1)
-0.07 9.93 library recovery time
9.93 data required time
-----------------------------------------------------------------------------
9.93 data required time
-2.01 data arrival time
-----------------------------------------------------------------------------
7.92 slack (MET)


Startpoint: _393206_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG
(rising clock gating-check end-point clocked by clk')
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _393206_/CLK (sky130_fd_sc_hd__dfrtp_1)
6.94 4.12 4.12 ^ _393206_/Q (sky130_fd_sc_hd__dfrtp_1)
7 0.82 dBusWB_CYC (net)
6.94 0.00 4.12 ^ _170980_/A1 (sky130_fd_sc_hd__a21oi_1)
1.00 0.53 4.65 v _170980_/Y (sky130_fd_sc_hd__a21oi_1)
3 0.01 _057163_ (net)
1.00 0.00 4.65 v _170984_/A2 (sky130_fd_sc_hd__o31a_1)
8.16 6.58 11.23 v _170984_/X (sky130_fd_sc_hd__o31a_1)
363 1.96 _057167_ (net)
8.18 0.36 11.59 v _171012_/A1 (sky130_fd_sc_hd__a21oi_1)
3.13 5.62 17.21 ^ _171012_/Y (sky130_fd_sc_hd__a21oi_1)
31 0.16 _057195_ (net)
3.13 0.00 17.21 ^ _174406_/A (sky130_fd_sc_hd__nand2_1)
0.73 0.75 17.96 v _174406_/Y (sky130_fd_sc_hd__nand2_1)
8 0.03 _059918_ (net)
0.73 0.00 17.96 v _174579_/B1 (sky130_fd_sc_hd__o2bb2ai_1)
1652.94 1197.18 1215.14 ^ _174579_/Y (sky130_fd_sc_hd__o2bb2ai_1)
13060 87.98 _060082_ (net)
1653.15 15.89 1231.03 ^ _174590_/A2 (sky130_fd_sc_hd__o21ai_0)
30.96 22197.20 23428.23 v _174590_/Y (sky130_fd_sc_hd__o21ai_0)
1024 4.50 IBusCachedPlugin_cache.ways_0_datas.adr[0] (net)
30.96 4.53 23432.76 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.DEC0.AND3/C (sky130_fd_sc_hd__and4b_2)
0.85 12.20 23444.96 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.DEC0.AND3/X (sky130_fd_sc_hd__and4b_2)
8 0.09 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[3].W.SEL0 (net)
0.85 0.00 23444.96 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.CGAND/A (sky130_fd_sc_hd__and2_1)
0.91 0.39 23445.36 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.CGAND/X (sky130_fd_sc_hd__and2_1)
1 0.00 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.WE0_WIRE (net)
0.91 0.00 23445.36 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/GATE (sky130_fd_sc_hd__dlclkp_1)
23445.36 data arrival time

0.00 5.00 5.00 clock clk' (rise edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 clock reconvergence pessimism
5.00 ^ IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/CLK (sky130_fd_sc_hd__dlclkp_1)
-0.36 4.64 library setup time
4.64 data required time
-----------------------------------------------------------------------------
4.64 data required time
-23445.36 data arrival time
-----------------------------------------------------------------------------
-23440.72 slack (VIOLATED)



==========================================================================
global place report_checks -unconstrained
--------------------------------------------------------------------------
Startpoint: externalResetVector[21] (input port clocked by clk)
Endpoint: _392885_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 0.00 v externalResetVector[21] (in)
2 0.78 externalResetVector[21] (net)
2.83 1.41 1.41 v _334904_/B (sky130_fd_sc_hd__nand2_1)
0.48 0.60 2.01 ^ _334904_/Y (sky130_fd_sc_hd__nand2_1)
1 0.00 _000345_ (net)
0.48 0.00 2.01 ^ _392885_/SET_B (sky130_fd_sc_hd__dfbbp_1)
2.01 data arrival time

0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ _392885_/CLK (sky130_fd_sc_hd__dfbbp_1)
-0.07 9.93 library recovery time
9.93 data required time
-----------------------------------------------------------------------------
9.93 data required time
-2.01 data arrival time
-----------------------------------------------------------------------------
7.92 slack (MET)


Startpoint: _393206_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG
(rising clock gating-check end-point clocked by clk')
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _393206_/CLK (sky130_fd_sc_hd__dfrtp_1)
6.94 4.12 4.12 ^ _393206_/Q (sky130_fd_sc_hd__dfrtp_1)
7 0.82 dBusWB_CYC (net)
6.94 0.00 4.12 ^ _170980_/A1 (sky130_fd_sc_hd__a21oi_1)
1.00 0.53 4.65 v _170980_/Y (sky130_fd_sc_hd__a21oi_1)
3 0.01 _057163_ (net)
1.00 0.00 4.65 v _170984_/A2 (sky130_fd_sc_hd__o31a_1)
8.16 6.58 11.23 v _170984_/X (sky130_fd_sc_hd__o31a_1)
363 1.96 _057167_ (net)
8.18 0.36 11.59 v _171012_/A1 (sky130_fd_sc_hd__a21oi_1)
3.13 5.62 17.21 ^ _171012_/Y (sky130_fd_sc_hd__a21oi_1)
31 0.16 _057195_ (net)
3.13 0.00 17.21 ^ _174406_/A (sky130_fd_sc_hd__nand2_1)
0.73 0.75 17.96 v _174406_/Y (sky130_fd_sc_hd__nand2_1)
8 0.03 _059918_ (net)
0.73 0.00 17.96 v _174579_/B1 (sky130_fd_sc_hd__o2bb2ai_1)
1652.94 1197.18 1215.14 ^ _174579_/Y (sky130_fd_sc_hd__o2bb2ai_1)
13060 87.98 _060082_ (net)
1653.15 15.89 1231.03 ^ _174590_/A2 (sky130_fd_sc_hd__o21ai_0)
30.96 22197.20 23428.23 v _174590_/Y (sky130_fd_sc_hd__o21ai_0)
1024 4.50 IBusCachedPlugin_cache.ways_0_datas.adr[0] (net)
30.96 4.53 23432.76 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.DEC0.AND3/C (sky130_fd_sc_hd__and4b_2)
0.85 12.20 23444.96 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.DEC0.AND3/X (sky130_fd_sc_hd__and4b_2)
8 0.09 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[3].W.SEL0 (net)
0.85 0.00 23444.96 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.CGAND/A (sky130_fd_sc_hd__and2_1)
0.91 0.39 23445.36 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.CGAND/X (sky130_fd_sc_hd__and2_1)
1 0.00 IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.WE0_WIRE (net)
0.91 0.00 23445.36 v IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/GATE (sky130_fd_sc_hd__dlclkp_1)
23445.36 data arrival time

0.00 5.00 5.00 clock clk' (rise edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 clock reconvergence pessimism
5.00 ^ IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[1].RAM128.BLOCK[2].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.genblk1.CG/CLK (sky130_fd_sc_hd__dlclkp_1)
-0.36 4.64 library setup time
4.64 data required time
-----------------------------------------------------------------------------
4.64 data required time
-23445.36 data arrival time
-----------------------------------------------------------------------------
-23440.72 slack (VIOLATED)



==========================================================================
global place report_tns
--------------------------------------------------------------------------
tns -57064752.00

==========================================================================
global place report_wns
--------------------------------------------------------------------------
wns -23440.72

==========================================================================
global place report_worst_slack
--------------------------------------------------------------------------
worst slack -23440.72

==========================================================================
global place report_clock_skew
--------------------------------------------------------------------------
Clock clk
Latency CRPR Skew
IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[2].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[6].genblk1.STORAGE/GATE ^
0.26
IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[2].RAM128.BLOCK[3].RAM32.Do0_FF[6]/CLK ^
0.00 0.00 0.26


==========================================================================
global place report_power
--------------------------------------------------------------------------
Group Internal Switching Leakage Total
Power Power Power Power
----------------------------------------------------------------
Sequential 4.25e-01 2.16e-02 9.12e-07 4.46e-01 12.3%
Combinational 2.73e+00 4.51e-01 8.63e-07 3.18e+00 87.7%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 3.15e+00 4.72e-01 1.77e-06 3.62e+00 100.0%
87.0% 13.0% 0.0%

==========================================================================
global place report_design_area
--------------------------------------------------------------------------
Design area 4874394 u^2 24% utilization.

Elapsed time: 14:19.41[h:]min:sec. CPU time: user 845.86 sys 13.41 (99%). Peak memory: 14352804KB.

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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/3_1_place_gp.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0094] Created 400000 Insts
[INFO ODB-0094] Created 500000 Insts
[INFO ODB-0094] Created 600000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 651926 components and 2587892 component-terminals.
[INFO ODB-0132] Created 2 special nets and 1303852 connections.
[INFO ODB-0133] Created 317870 nets and 1283758 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/3_1_place_gp.def
Found 0 macro blocks.
Using 1u default distance from corners.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0010] Tentative 0 to set up sections.
[INFO PPL-0001] Number of slots 18082
[INFO PPL-0002] Number of I/O 254
[INFO PPL-0003] Number of I/O w/sink 254
[INFO PPL-0004] Number of I/O w/o sink 7
[INFO PPL-0005] Slots per section 200
[INFO PPL-0006] Slots increase factor 0.01
[INFO PPL-0008] Successfully assigned pins to sections.
[INFO PPL-0012] I/O nets HPWL: 311666.22 um.
Elapsed time: 0:11.63[h:]min:sec. CPU time: user 11.04 sys 0.55 (99%). Peak memory: 1537160KB.

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OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/4_1_cts.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0094] Created 400000 Insts
[INFO ODB-0094] Created 500000 Insts
[INFO ODB-0094] Created 600000 Insts
[INFO ODB-0094] Created 700000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 254 pins.
[INFO ODB-0131] Created 700326 components and 2781492 component-terminals.
[INFO ODB-0132] Created 2 special nets and 1400652 connections.
[INFO ODB-0133] Created 366270 nets and 1375112 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/4_1_cts.def
[INFO DPL-0001] Placed 1989750 filler instances.
Elapsed time: 0:21.72[h:]min:sec. CPU time: user 20.88 sys 0.81 (99%). Peak memory: 2430564KB.

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"drt::wire length::total" : 22150044
, "drt::vias::total" : 3157600
}

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[INFO] Reporting cells prior to loading DEF ...
[INFO] Reading DEF ...
[INFO] Clearing cells...
[INFO] ... preserving 'VIA_L1M1_PR'
[INFO] ... preserving 'VIA_L1M1_PR_R'
[INFO] ... preserving 'VIA_L1M1_PR_M'
[INFO] ... preserving 'VIA_L1M1_PR_MR'
[INFO] ... preserving 'VIA_L1M1_PR_C'
[INFO] ... preserving 'VIA_M1M2_PR'
[INFO] ... preserving 'VIA_M1M2_PR_R'
[INFO] ... preserving 'VIA_M1M2_PR_M'
[INFO] ... preserving 'VIA_M1M2_PR_MR'
[INFO] ... preserving 'VIA_M1M2_PR_C'
[INFO] ... preserving 'VIA_M2M3_PR'
[INFO] ... preserving 'VIA_M2M3_PR_R'
[INFO] ... preserving 'VIA_M2M3_PR_M'
[INFO] ... preserving 'VIA_M2M3_PR_MR'
[INFO] ... preserving 'VIA_M2M3_PR_C'
[INFO] ... preserving 'VIA_M3M4_PR'
[INFO] ... preserving 'VIA_M3M4_PR_R'
[INFO] ... preserving 'VIA_M3M4_PR_M'
[INFO] ... preserving 'VIA_M3M4_PR_MR'
[INFO] ... preserving 'VIA_M3M4_PR_C'
[INFO] ... preserving 'VIA_M4M5_PR'
[INFO] ... preserving 'VIA_M4M5_PR_R'
[INFO] ... preserving 'VIA_M4M5_PR_M'
[INFO] ... preserving 'VIA_M4M5_PR_MR'
[INFO] ... preserving 'VIA_M4M5_PR_C'
[INFO] ... preserving 'VIA_via_1600x480'
[INFO] ... preserving 'VIA_via2_1600x480'
[INFO] ... preserving 'VIA_via3_1600x480'
[INFO] ... preserving 'VIA_via4_1600x1600'
[INFO] Merging GDS/OAS files...
./platforms/sky130hd/gds/sky130_fd_sc_hd.gds
[INFO] Copying toplevel cell 'A2P_WB'
INFO: Reading config file: ./platforms/sky130hd/fill.json
[INFO] Checking for missing cell from GDS/OAS...
[INFO] All LEF cells have matching GDS/OAS cells
[INFO] Checking for orphan cell in the final layout...
[INFO] No orphan cells
[INFO] Writing out GDS/OAS 'results/sky130hd/a2p/base/6_1_merged.gds'
Elapsed time: 0:54.45[h:]min:sec. CPU time: user 51.40 sys 2.41 (98%). Peak memory: 6525240KB.

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