Log the instruction read from the icache, not the instruction (if any)
being written to the icache.
Fixes: 6db626d245 ("icache: Log 36 bits of instruction rather than 32")
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This adds a new type of stop trigger for the log buffer which triggers
when any byte(s) of a specified doubleword of memory are written.
The trigger logic snoops the wishbone for writes to the address
specified and stops the log 256 cycles later (same as for the
instruction fetch address trigger). The trigger address is a real
address and sees DMA writes from devices as well as stores done by the
CPU.
The mw_debug command has a new 'mtrig' subcommand to set the trigger
and query its state.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
With this, the logic that maintains r1.acks_pending operates in every
state based on r1.wb and wishbone_in, rather than only operating in
STORE_WAIT_ACK state. This makes things a bit clearer and improves
timing slightly.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Make the shield I/O pins be individual signals rather than a bus in
order to avoid warnings on pins which don't have both a driver and a
receiver.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This implements the byte-reverse halfword, word and doubleword
instructions: brh, brw, and brd. These instructions were added to the
ISA in version 3.1. They use a new OP_BREV insn_type value. The
logic for these instructions is implemented in logical.vhdl.
In order to avoid going over 64 insn_type values, OP_AND and OP_OR
were combined into OP_LOGIC, which is like OP_AND except that the RS
input can be inverted as well as the RB input. The various forms of
OR instruction are then implemented using the identity
a OR b = NOT (NOT a AND NOT b)
The 'is_signed' field of the instruction decode table is used to
indicate that RS should be inverted.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This implements the setbc, setnbc, setbcr and setnbcr instructions.
Because the insn_type_t type already has 64 elements, this uses the
existing OP_SETB for the new instructions, and has execute1 compute
different results depending on bits 6-9 of the instruction.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This arranges to generate an illegal instruction type program
interrupt for illegal prefixed instructions, that is, those where the
suffix is not a legal value given the prefix, or the prefix has a
reserved value in the subtype field. This implementation doesn't
generate an interrupt for the invalid 8LS:D and MLS:D instruction
forms where R = 1 and RA != 0. (In those cases it uses (RA) as the
addend, i.e. it ignores the R bit.)
This detects the case where the address of an instruction prefix is
equal mod 64 to 60, and generates an alignment interrupt in that case.
This also arranges to set bit 34 of SRR1 when an interrupt occurs due
to a prefixed instruction, for those interrupts where that is required
(i.e. trace, alignment, floating-point unavailable, data storage, data
segment, and most cases of program interrupt).
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This adds logic to do basic decoding of the prefixed instructions
defined in PowerISA v3.1B which are in the SFFS (Scalar Fixed plus
Floating-Point Subset) compliancy subset. In PowerISA v3.1B SFFS,
there are 14 prefixed load/store instructions plus the prefixed no-op
instruction (pnop). The prefixed load/store instructions all use an
extended version of D-form, which has an extra 18 bits of displacement
in the prefix, plus an 'R' bit which enables PC-relative addressing.
When decode1 sees an instruction word where the insn_code is
INSN_prefix (i.e. the primary opcode was 1), it stores the prefix word
and sends nothing down to decode2 in that cycle. When the next valid
instruction word arrives, it is interpreted as a suffix, meaning that
its insn_code gets modified before being used to look up the decode
table.
The insn_code values are rearranged so that the values for
instructions which are the suffix of a valid prefixed instruction are
all at even indexes, and the corresponding prefixed instructions
follow immediately, so that an insn_code value can be converted to the
corresponding prefixed value by setting the LSB of the insn_code
value. There are two prefixed instructions, pld and pstd, for which
the suffix is not a valid SFFS instruction by itself, so these have
been given dummy insn_code values which decode as illegal (INSN_op57
and INSN_op61).
For a prefixed instruction, decode1 examines the type and subtype
fields of the prefix and checks that the suffix is valid for the type
and subtype. This check doesn't affect which entry of the decode
table is used; the result is passed down to decode2, and will in
future be acted upon in execute1.
The instruction address passed down to decode2 is the address of the
prefix. To enable this, part of the instruction address is saved when
the prefix is seen, and then the instruction address received from
icache is partly overlaid by the saved prefix address. Because
prefixed instructions are not permitted to cross 64-byte boundaries,
we only need to save bits 5:2 of the instruction to do this. If the
alignment restriction ever gets relaxed, we will then need to save
more bits of the address.
Decode2 has been extended to handle the R bit of the prefix (in 8LS
and MLS forms) and to be able to generate the 34-bit immediate value
from the prefix and suffix.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This moves the insn_code values for mcrfs, mtfsb0/1 and mtfsfi into
the region used for floating-point instructions. This means that in
no-FPU implementations, they will get turned into illegal instructions
in predecode. We then don't need the code in execute1 that makes FP
instructions illegal in no-FPU implementations.
We also remove the NONE value for unit_t, since it was only ever used
with insn_type = OP_ILLEGAL, and the check for unit = NONE was
redundant with the check for insn_type = OP_ILLEGAL. Thus the check
for unit = NONE is no longer needed and is removed here.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Instead of sending down the predicted taken/not-taken bits with the
target of the branch, we now send them down with the branch itself.
Previously icache adjusted for this by sending the prediction bits to
decode1 without a 1-clock delay while everything else had a 1-clock
delay. Now icache keeps the prediction bits with the rest of the
attributes for the request.
Also fix a buglet in fetch1 where the first address sent out after
reset didn't have .req set. Currently this doesn't cause a problem
because icache doesn't really look at .req.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
The soc itself will be reset when a syscon soc reset is triggered.
Separately, top- board files can use the sw_soc_rst signal
if they need to reset other peripherals
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Using
litedram c770dd62edc281c370f9e2c694fe4ac1525a0b4a
litex e570b612b2a9d8f8d2002d79497bda0dc35b936a
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Instead of connecting core_alt_reset to litedram init_done, it moves to
a syscon register bit. This simplifies top- files and future soc_reset
handling. sdram main.c can unset the alt_reset bit after sdram init.
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Treat the input as if it was padded with zeroes to a multiple
of 8. This is needed if the .data in a binary changes size, it
won't be a nice multiple of 4 or 8. At present the microwatt
binaries all are multiples of 8, but making code alterations could make
bin2hex fail unexpectedly.
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
We already carry the UART verilog source, so we may as well use it
instead of requiring fusesoc to import it from its library
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This reworks (and simplifies) plru_tb to use the new plrufn module
instead of the old (and now unused) plru module.
The latter is now removed completely.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The IO bridge would latch the top half of write data and selection signals
when issuing the second downstream store. Unfortunately at this point the
bridge has already "accepted" the upstream store from the core (due to
stall being 0 on the cycle when stb/cyc are 1), so the values on the
wishbone signals aren't stable and might already reflect a subsequent
wishbone command.
This causes occasional data corruption of 64-bit stores through the IO
bridge.
While at it, take out a bunch of useless conditions on the data latch
path. It doesn't matter whether we is 0 or 1, we can just always latch
the data, the destination will decide whether to use the content or not,
which should save a bit of hardware.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Allows to trigger on rising/falling/both edge, as well
as high/low level.
Registers are compatible with Linux ftgpio010 driver.
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
The current dcache will not update the PLRU on a cache miss which is later
satisfied during the reload process. Thus subsequent misses will potentially
evict the same cache line. The same issue happens with dcbz which are
treated more/less as load misses.
This fixes it by triggering a PLRU update when r1.choose_victim, which is
set on a miss for one cycle to snapshot the PLRU output. This means we will
update the PLRU on the same cycle as we capture its output, which is fine
(the new value will be visible on the next cycle).
That way, a "miss" will result in a PLRU update to reflect that the entry
being refilled is actually used (and will be used to serve subsequent
load operations from the same cache line while being refilled).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
It bitrotted... more signals need to be initialized. This also adds
a lot more accesses with different timing conditions allowing to
test cases of hit during reloads, hit with reload formward, hit on idle
cache etc...
It also exposes a bug where the cache miss caused by the read of 0x140
uses the same victim way as previous cache miss of 0x40 (same index).
This bug will need to be fixed separately, but at least this exposes it.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Starting from 5e7612eb4, OpenOCD identifies itself as 0.12.
This causes Microwatt's flash-arty script to fail. Because neither
the cfg nor the proxy bitstream are affected, we can keep treating
everything as indistinguishable from 0.11. This patch simply tests
for "0.12" as an alias; it would probably be better to replace this
confusing terminology with something like "single-tap/multi-tap".
Signed-off-by: Boris Shingarov <shingarov@labware.com>
This includes the cable configuration, additions to the Python script,
and the jtagspi proxy bitstream. The single-tap version is not included
because 0.10 supported only 3-byte addresses which is unusable on the
s25fl256s anyway.
Signed-off-by: Boris Shingarov <shingarov@labware.com>
As has been done for the L1 dcache and icache, this puts the L2 cache
PLRU state into a little RAM and has a single copy of the logic to
calculate the pseudo-LRU way and update the PLRU state.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Rather than having update and decode logic for each individual PLRU
as well as a register to store the current PLRU state, we now put the
PLRU state in a little RAM, which will typically use LUT RAM on FPGAs,
and have just a single copy of the logic to calculate the pseudo-LRU
way and to update the PLRU state.
The PLRU RAM that apples to the data storage (as opposed to the TLB)
is read asynchronously in the cycle after the cache tag matching is
done. At the end of that cycle the PLRU RAM entry is updated if the
access was a cache hit, or a victim way is calculated and stored if
the access was a cache miss. It is possible that a cache miss doesn't
start being handled until later, in which case the stored victim way
is used later when the miss gets handled.
Similarly for the TLB PLRU, the RAM is read asynchronously in the
cycle after a TLB lookup is done, and either updated at the end of
that cycle (for a hit), or a victim is chosen and stored for when the
TLB miss is satisfied.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras
Anton Blanchard
Michael Neuling