openpowerwtf
|
7fd72767b8
|
change verilator publics
|
2 years ago |
|
openpowerwtf
|
ba43fff83c
|
add wires
|
2 years ago |
|
openpowerwtf
|
4742892965
|
rewrite trilib
|
2 years ago |
|
openpowerwtf
|
c2914f2576
|
issue 11: verilator
|
2 years ago |
|
openpowerwtf
|
0e55fb9697
|
fix datr_d numbering
|
2 years ago |
|
openpowerwtf
|
7256fa3539
|
parm experiments and cleanup
|
2 years ago |
|
openpowerwtf
|
1562980638
|
start litex version
|
2 years ago |
|
openpowerwtf
|
c82f7a3330
|
add wishbone interface
|
2 years ago |
|
openpowerwtf
|
2bc49c945b
|
yosys cleanup
|
2 years ago |
|
openpowerwtf
|
b0efaecf46
|
verilator comments
|
2 years ago |
|
openpowerwtf
|
7043a1645b
|
inits to disable cg
|
2 years ago |
|
openpowerwtf
|
1d003f8822
|
cleanup
|
2 years ago |
|
openpowerwtf
|
11724a1c12
|
tie pervasive sigs in rtl
|
2 years ago |
|
openpowerwtf
|
200551679c
|
syntax
|
2 years ago |
|
openpowerwtf
|
1cefef0726
|
get rid of some gen begin/end msgs
|
2 years ago |
|
openpowerwtf
|
0dcb681aad
|
start a2l2wb
|
2 years ago |
|
Bill Flynn
|
6df9adebdd
|
node
|
2 years ago |
|
openpowerwtf
|
975bb2445d
|
make mem visible in iverilog dump
|
2 years ago |
|
openpowerwtf
|
173e1ad5f1
|
fix x's on unused t1 strands
|
2 years ago |
|
openpowerwtf
|
3893e0253d
|
add dev
|
2 years ago |