With this, the logic that maintains r1.acks_pending operates in every
state based on r1.wb and wishbone_in, rather than only operating in
STORE_WAIT_ACK state. This makes things a bit clearer and improves
timing slightly.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Make the shield I/O pins be individual signals rather than a bus in
order to avoid warnings on pins which don't have both a driver and a
receiver.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
The soc itself will be reset when a syscon soc reset is triggered.
Separately, top- board files can use the sw_soc_rst signal
if they need to reset other peripherals
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Using
litedram c770dd62edc281c370f9e2c694fe4ac1525a0b4a
litex e570b612b2a9d8f8d2002d79497bda0dc35b936a
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Instead of connecting core_alt_reset to litedram init_done, it moves to
a syscon register bit. This simplifies top- files and future soc_reset
handling. sdram main.c can unset the alt_reset bit after sdram init.
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Treat the input as if it was padded with zeroes to a multiple
of 8. This is needed if the .data in a binary changes size, it
won't be a nice multiple of 4 or 8. At present the microwatt
binaries all are multiples of 8, but making code alterations could make
bin2hex fail unexpectedly.
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
We already carry the UART verilog source, so we may as well use it
instead of requiring fusesoc to import it from its library
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This reworks (and simplifies) plru_tb to use the new plrufn module
instead of the old (and now unused) plru module.
The latter is now removed completely.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The IO bridge would latch the top half of write data and selection signals
when issuing the second downstream store. Unfortunately at this point the
bridge has already "accepted" the upstream store from the core (due to
stall being 0 on the cycle when stb/cyc are 1), so the values on the
wishbone signals aren't stable and might already reflect a subsequent
wishbone command.
This causes occasional data corruption of 64-bit stores through the IO
bridge.
While at it, take out a bunch of useless conditions on the data latch
path. It doesn't matter whether we is 0 or 1, we can just always latch
the data, the destination will decide whether to use the content or not,
which should save a bit of hardware.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Allows to trigger on rising/falling/both edge, as well
as high/low level.
Registers are compatible with Linux ftgpio010 driver.
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
The current dcache will not update the PLRU on a cache miss which is later
satisfied during the reload process. Thus subsequent misses will potentially
evict the same cache line. The same issue happens with dcbz which are
treated more/less as load misses.
This fixes it by triggering a PLRU update when r1.choose_victim, which is
set on a miss for one cycle to snapshot the PLRU output. This means we will
update the PLRU on the same cycle as we capture its output, which is fine
(the new value will be visible on the next cycle).
That way, a "miss" will result in a PLRU update to reflect that the entry
being refilled is actually used (and will be used to serve subsequent
load operations from the same cache line while being refilled).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
It bitrotted... more signals need to be initialized. This also adds
a lot more accesses with different timing conditions allowing to
test cases of hit during reloads, hit with reload formward, hit on idle
cache etc...
It also exposes a bug where the cache miss caused by the read of 0x140
uses the same victim way as previous cache miss of 0x40 (same index).
This bug will need to be fixed separately, but at least this exposes it.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Starting from 5e7612eb4, OpenOCD identifies itself as 0.12.
This causes Microwatt's flash-arty script to fail. Because neither
the cfg nor the proxy bitstream are affected, we can keep treating
everything as indistinguishable from 0.11. This patch simply tests
for "0.12" as an alias; it would probably be better to replace this
confusing terminology with something like "single-tap/multi-tap".
Signed-off-by: Boris Shingarov <shingarov@labware.com>
This includes the cable configuration, additions to the Python script,
and the jtagspi proxy bitstream. The single-tap version is not included
because 0.10 supported only 3-byte addresses which is unusable on the
s25fl256s anyway.
Signed-off-by: Boris Shingarov <shingarov@labware.com>
As has been done for the L1 dcache and icache, this puts the L2 cache
PLRU state into a little RAM and has a single copy of the logic to
calculate the pseudo-LRU way and update the PLRU state.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Rather than having update and decode logic for each individual PLRU
as well as a register to store the current PLRU state, we now put the
PLRU state in a little RAM, which will typically use LUT RAM on FPGAs,
and have just a single copy of the logic to calculate the pseudo-LRU
way and to update the PLRU state.
The PLRU RAM that apples to the data storage (as opposed to the TLB)
is read asynchronously in the cycle after the cache tag matching is
done. At the end of that cycle the PLRU RAM entry is updated if the
access was a cache hit, or a victim way is calculated and stored if
the access was a cache miss. It is possible that a cache miss doesn't
start being handled until later, in which case the stored victim way
is used later when the miss gets handled.
Similarly for the TLB PLRU, the RAM is read asynchronously in the
cycle after a TLB lookup is done, and either updated at the end of
that cycle (for a hit), or a victim is chosen and stored for when the
TLB miss is satisfied.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Rather than having update and decode logic for each individual PLRU
as well as a register to store the current PLRU state, we now put the
PLRU state in a little RAM, which will typically use LUT RAM on FPGAs,
and have just a single copy of the logic to calculate the pseudo-LRU
way and to update the PLRU state. This logic is in the plrufn module
and is just combinatorial logic. A new module was created for this as
other parts of the system are still using plru.vhdl.
The PLRU RAM in the icache is read asynchronously in the cycle
after the cache tag matching is done. At the end of that cycle the
PLRU RAM entry is updated if the access was a cache hit, or a victim
way is calculated and stored if the access was a cache miss and
miss handling is starting in this cycle.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This fixes a couple of build warnings in litedram-wrapper-l2.vhdl
litedram/extras/litedram-wrapper-l2.vhdl:552:17⚠️ declaration of "i" hides constant "i" [-Whide]
for i in 0 to ROW_SIZE-1 loop
^
litedram/extras/litedram-wrapper-l2.vhdl:1129:9⚠️ declaration of "litedram_trace" hides generic "litedram_trace" [-Whide]
litedram_trace: litedram_trace_stub;
^
It also cleans up the runtime metavalue warnings
Signed-off-by: Michael Neuling <mikey@neuling.org>
We disabled --trace by default, so we need to stop linking verilated_vcd_c.o
as it doesn't exist in that case.
While at it, make a Makefile variable to enable/disable verilator tracing
and add a couple of generics to those test benches to control tracing
in the L2 and in litedram.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The Antmicro Artix DC-SCM uses the following FTDI part:
0403:6011 Future Technology Devices International, Ltd FT4232H Quad HS USB-UART/FIFO IC
To use:
$ openocd/flash-arty -c antmicro-artix-dc-scm -f a100 -t bin -a 0x300000 ~/u-boot
Signed-off-by: Joel Stanley <joel@jms.id.au>
As with the DRAM configuration, the DC-SCM board uses the same PHY as
the Nexys Video and works with it's generated VHDL.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Paul Mackerras
Anton Blanchard
Michael Neuling