Commit Graph

1263 Commits (d299ea925ec1110cafc9ebbf48a53031815e1f28)
 

Author SHA1 Message Date
Benjamin Herrenschmidt d299ea925e Bundle the uart16550 core file
We already carry the UART verilog source, so we may as well use it
instead of requiring fusesoc to import it from its library

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
12 months ago
Michael Neuling 432d9f3150
Merge pull request #413 from ozbenh/fix-io-bridge-qw-store
soc: Fix issues with 64-bit stores to IO bridge
12 months ago
Benjamin Herrenschmidt 3f788e87dc soc: Fix issues with 64-bit stores to IO bridge
The IO bridge would latch the top half of write data and selection signals
when issuing the second downstream store. Unfortunately at this point the
bridge has already "accepted" the upstream store from the core (due to
stall being 0 on the cycle when stb/cyc are 1), so the values on the
wishbone signals aren't stable and might already reflect a subsequent
wishbone command.

This causes occasional data corruption of 64-bit stores through the IO
bridge.

While at it, take out a bunch of useless conditions on the data latch
path. It doesn't matter whether we is 0 or 1, we can just always latch
the data, the destination will decide whether to use the content or not,
which should save a bit of hardware.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
12 months ago
Paul Mackerras 413f2dc5d6
Merge pull request #411 from ozbenh/dcache-plru-update-fix
Dcache PLRU update fix
1 year ago
Benjamin Herrenschmidt 76f61ef823 dcache: Update PLRU on misses as well as hits
The current dcache will not update the PLRU on a cache miss which is later
satisfied during the reload process. Thus subsequent misses will potentially
evict the same cache line. The same issue happens with dcbz which are
treated more/less as load misses.

This fixes it by triggering a PLRU update when r1.choose_victim, which is
set on a miss for one cycle to snapshot the PLRU output. This means we will
update the PLRU on the same cycle as we capture its output, which is fine
(the new value will be visible on the next cycle).

That way, a "miss" will result in a PLRU update to reflect that the entry
being refilled is actually used (and will be used to serve subsequent
load operations from the same cache line while being refilled).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
1 year ago
Benjamin Herrenschmidt 3edbbf5f18 Fix dcache_tb (and add dump of victim way to dcache)
It bitrotted... more signals need to be initialized. This also adds
a lot more accesses with different timing conditions allowing to
test cases of hit during reloads, hit with reload formward, hit on idle
cache etc...

It also exposes a bug where the cache miss caused by the read of 0x140
uses the same victim way as previous cache miss of 0x40 (same index).

This bug will need to be fixed separately, but at least this exposes it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
1 year ago
Michael Neuling 84a0fba25d
Merge pull request #408 from paulusmack/plru-improvement
PLRU improvements
1 year ago
Michael Neuling 5766dbab37
Merge pull request #406 from shingarov/spi-kintex
Add support for flashing the s25fl256s onboard Genesys2
1 year ago
Michael Neuling d9c55defdb
Merge pull request #407 from shingarov/openocd-012
Recognize version string "0.12" in recent OpenOCD master
1 year ago
Boris Shingarov ed5807381e Recognize version string "0.12" in recent OpenOCD master
Starting from 5e7612eb4, OpenOCD identifies itself as 0.12.
This causes Microwatt's flash-arty script to fail.  Because neither
the cfg nor the proxy bitstream are affected, we can keep treating
everything as indistinguishable from 0.11.  This patch simply tests
for "0.12" as an alias; it would probably be better to replace this
confusing terminology with something like "single-tap/multi-tap".

Signed-off-by: Boris Shingarov <shingarov@labware.com>
1 year ago
Boris Shingarov 6c3f7d75d5 Add support for flashing the s25fl256s onboard Genesys2
This includes the cable configuration, additions to the Python script,
and the jtagspi proxy bitstream. The single-tap version is not included
because 0.10 supported only 3-byte addresses which is unusable on the
s25fl256s anyway.

Signed-off-by: Boris Shingarov <shingarov@labware.com>
1 year ago
Paul Mackerras b8f9c833f8 litedram: Split L2 PLRU into storage and logic
As has been done for the L1 dcache and icache, this puts the L2 cache
PLRU state into a little RAM and has a single copy of the logic to
calculate the pseudo-LRU way and update the PLRU state.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
1 year ago
Paul Mackerras a1f5867919 dcache: Split PLRU into storage and logic
Rather than having update and decode logic for each individual PLRU
as well as a register to store the current PLRU state, we now put the
PLRU state in a little RAM, which will typically use LUT RAM on FPGAs,
and have just a single copy of the logic to calculate the pseudo-LRU
way and to update the PLRU state.

The PLRU RAM that apples to the data storage (as opposed to the TLB)
is read asynchronously in the cycle after the cache tag matching is
done.  At the end of that cycle the PLRU RAM entry is updated if the
access was a cache hit, or a victim way is calculated and stored if
the access was a cache miss.  It is possible that a cache miss doesn't
start being handled until later, in which case the stored victim way
is used later when the miss gets handled.

Similarly for the TLB PLRU, the RAM is read asynchronously in the
cycle after a TLB lookup is done, and either updated at the end of
that cycle (for a hit), or a victim is chosen and stored for when the
TLB miss is satisfied.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
1 year ago
Paul Mackerras 86212dc879 icache: Split PLRU into storage and logic
Rather than having update and decode logic for each individual PLRU
as well as a register to store the current PLRU state, we now put the
PLRU state in a little RAM, which will typically use LUT RAM on FPGAs,
and have just a single copy of the logic to calculate the pseudo-LRU
way and to update the PLRU state.  This logic is in the plrufn module
and is just combinatorial logic.  A new module was created for this as
other parts of the system are still using plru.vhdl.

The PLRU RAM in the icache is read asynchronously in the cycle
after the cache tag matching is done.  At the end of that cycle the
PLRU RAM entry is updated if the access was a cache hit, or a victim
way is calculated and stored if the access was a cache miss and
miss handling is starting in this cycle.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
1 year ago
Anton Blanchard d3fb2639dd
Merge pull request #403 from mikey/litedram-warnings
Fix litedram wrapper build warnings and metavalues
1 year ago
Paul Mackerras cd2e174113 dcache: Fix compilation with NUM_WAYS and/or TLB_NUM_WAYS = 1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
1 year ago
Paul Mackerras 82c8b2eae0 icache: Fix compilation with NUM_WAYS = 1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
1 year ago
Michael Neuling 24d04ed8f9 Fix litedram wrapper build warnings and metavalues
This fixes a couple of build warnings in litedram-wrapper-l2.vhdl

litedram/extras/litedram-wrapper-l2.vhdl:552:17⚠️ declaration of "i" hides constant "i" [-Whide]
            for i in 0 to ROW_SIZE-1 loop
                ^
litedram/extras/litedram-wrapper-l2.vhdl:1129:9⚠️ declaration of "litedram_trace" hides generic "litedram_trace" [-Whide]
        litedram_trace: litedram_trace_stub;
        ^

It also cleans up the runtime metavalue warnings

Signed-off-by: Michael Neuling <mikey@neuling.org>
1 year ago
Michael Neuling 047f739b58
Merge pull request #402 from ozbenh/misc
Fix core_dram_tb and dram_tb
1 year ago
Benjamin Herrenschmidt 39c2abae51 Fix build of core_dram_tb and dram_tb and fix tracing
We disabled --trace by default, so we need to stop linking verilated_vcd_c.o
as it doesn't exist in that case.

While at it, make a Makefile variable to enable/disable verilator tracing
and add a couple of generics to those test benches to control tracing
in the L2 and in litedram.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
1 year ago
Benjamin Herrenschmidt e31a4f7a9a Ignore vunit_out in git
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
1 year ago
Michael Neuling cb11ad8e64
Merge pull request #401 from shenki/dcscm
Add Antmicro Artix DC-SCM support
1 year ago
Joel Stanley ad858995aa openocd: Add Artix DC-SCM cable type
The Antmicro Artix DC-SCM uses the following FTDI part:

 0403:6011 Future Technology Devices International, Ltd FT4232H Quad HS USB-UART/FIFO IC

To use:

 $ openocd/flash-arty -c antmicro-artix-dc-scm -f a100 -t bin -a 0x300000 ~/u-boot

Signed-off-by: Joel Stanley <joel@jms.id.au>
1 year ago
Joel Stanley 13aa52dfa7 antmicro-artix-dc-scm: Add liteeth
As with the DRAM configuration, the DC-SCM board uses the same PHY as
the Nexys Video and works with it's generated VHDL.

Signed-off-by: Joel Stanley <joel@jms.id.au>
1 year ago
Joel Stanley e2ae325d5c antmicro-artix-dc-scm: Add Ethernet pins
Signed-off-by: Joel Stanley <joel@jms.id.au>
1 year ago
Joel Stanley 87a875b940 antmicro-artix-dc-scm: Enable SPI flash
Load from 3MB as the flash is only 4MB on this board.

Signed-off-by: Joel Stanley <joel@jms.id.au>
1 year ago
Joel Stanley 7065434652 antmicro-artix-dc-scm: Formatting to match top-arty
Make it easier to follow what needs to be updated.

Signed-off-by: Joel Stanley <joel@jms.id.au>
1 year ago
Joel Stanley 621da8106f antmicro-artix-dc-scm: Add SPI flash pins
Signed-off-by: Joel Stanley <joel@jms.id.au>
1 year ago
Joel Stanley fdc44a71a0 antmicro-artix-dc-scm: Update DRAM properties
Most pins are set to SSTL15, but litex generates SSTL135.

This should silence a vivado warning.

Signed-off-by: Joel Stanley <joel@jms.id.au>
1 year ago
Paul Mackerras 9b184ff569 antmicro-artix-dc-scm: Add DRAM support
This uses the exact same gateware as the nexys video, since the DRAM
connection is identical to the nexys video down to the pin assignments
on the FPGA.  The only minor difference is that the DRAM chip on the
dc-scm is a MT41K256M16TW vs. a ...HA part on the nexys video.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
[joel: rebase and tweaks]
Signed-off-by: Joel Stanley <joel@jms.id.au>
1 year ago
Michael Neuling d92af779eb Add Antmicro Artix DC SCM hello world support
works with:
 fusesoc build --target=antmicro-artix-dc-scm microwatt --ram_init_file=../hello_world/hello_world.hex

Signed-off-by: Michael Neuling <mikey@neuling.org>
[joel: Fixes and updates]
Signed-off-by: Joel Stanley <joel@jms.id.au>
1 year ago
Anton Blanchard 26095986f3
Merge pull request #400 from mikey/githash
syscon: Implement a register for storing git hash info
1 year ago
Michael Neuling cf6d57b803
Merge pull request #399 from ozbenh/misc
Fix PLRU
1 year ago
Dan Horák bd5e4bafba hello_world: Debug print the gitinfo syscon register
.oOOo.
 ."      ".
 ;  .mw.  ;   Microwatt, it works.
  . '  ' .
   \ || /     HDL Git SHA1: 211d23c4ad4fb5-dirty
    ;..;
    ;..;
    `ww'

Signed-off-by: Dan Horák <dan@danny.cz>
Signed-off-by: Michael Neuling <mikey@neuling.org>
1 year ago
Dan Horák 1ddbacb67f syscon: Implement a register for storing git hash info
It also stores the dirty status so that's known.

This does some Makefile tricks so that we only rebuild when the git
hash changes. This avoids rebuilding the world every time we run
make.

Also adds fusesoc generator, so that should continue to work as
before.

Signed-off-by: Dan Horák <dan@danny.cz>
Signed-off-by: Michael Neuling <mikey@neuling.org>
1 year ago
Benjamin Herrenschmidt fa4baa2800 Fix PLRU
Jacob Lifshay found a couple of issues with the PLRU implementation:

 - The tree array is one bit too long. This is harmless as this bit is never
accessed and thus should be optimized out

 - The PLRU read is using the wrong nodes when going down the tree, which leads
to incorrect results.

This fixes it and improves the test bench a bit. I have verified the expected
output using a hand-written tree states, observed the mismatch with the
current implementation and verified the fix.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
1 year ago
Anton Blanchard 050185e2ca
Merge pull request #397 from mikey/metavalue-counts
tests: Update metavalues test count
1 year ago
Michael Neuling 116f6281a9 tests: Update metavalues test count
With Paulus changes in PR #396 merged in 5c6d57de30, we can now reduce
the metavalue test counts.

Signed-off-by: Michael Neuling <mikey@neuling.org>
1 year ago
Michael Neuling 5c6d57de30
Merge pull request #396 from paulusmack/reduce-meta
Reduce metavalue warnings
1 year ago
Paul Mackerras 6fa468ca3d execute1: Reduce metavalue warnings
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
1 year ago
Paul Mackerras 0279b923ba loadstore1: Reduce metavalue warnings
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
1 year ago
Paul Mackerras a2d391dcae decode2: Reduce metavalue warnings
Explicitly check for undefined values and propagate them.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
1 year ago
Paul Mackerras 4fcc2500c2 core_debug: Reduce metavalue warnings
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
1 year ago
Paul Mackerras 221a7b3df0 icache: Reduce metavalue warnings
As in dcache, this changes most signals declared with integer type to
be unsigned bit vectors instead.  Some code has been rearranged to do
to_integer() or equality comparisons only when the relevant signals
should be well defined.  Non-fatal asserts have been sprinkled
throughout to assist with determining the cause of warnings from
library functions (primarily NUMERIC_STD.TO_INTEGER and
NUMERIC_STD."=").

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
1 year ago
Paul Mackerras 6fe9dc9640 dcache: Reduce metavalue warnings
Among other changes, this makes the things that were previously
declared as signals of integer base type to be unsigned, since
unsigned can carry metavalues, and hence we can get the checking for
metavalues closer to the uses and therefore restrict the checking to
the situations where the signal really ought to be well defined.
We now have a couple more signals that indicate request validity to
help with that.

Non-fatal asserts have been sprinkled throughout to assist with
determining the cause of warnings from library functions (primarily
NUMERIC_STD.TO_INTEGER and NUMERIC_STD."=").

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
1 year ago
Michael Neuling ff63ffdbfd
Merge pull request #382 from paulusmack/master
Decode in block RAM and other improvements
1 year ago
Michael Neuling 0073d23e73
Merge pull request #392 from paulusmack/fix-branch-alias
fetch1: Fix bug where BTC entries don't match on MSR[IR]
1 year ago
Paul Mackerras 20f49f06f8 multiply_tb: Fix multiply_tb.vhdl for the new multiplier interface
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
1 year ago
Paul Mackerras b0aa5340b8 execute1: Make it clear that divide logic is not included when HAS_FPU=true
This adds a "not HAS_FPU" condition in a few places to make it obvious
that logic to interface to the divide unit is not included when we
have an FPU.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
1 year ago
Paul Mackerras d1e8e62fee Remove option for "short" 16x16 bit multiplier
Now that we have a 33 bit x 33 bit signed multiplier in execute1,
there is really no need for the 16 bit multiplier.  The coremark
results are just as good without it as with it.  This removes the
option for the sake of simplicity.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
1 year ago