A tiny Open POWER ISA softcore written in VHDL 2008
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Paul Mackerras 622f8c81cc loadstore1: Fix setting of SRR0 on alignment interrupt
When an alignment interrupt was being generated, loadstore1 was
setting the l_out.valid signal in one cycle and l_out.interrupt in the
next, for the same instruction.  This meant that the offending
instruction completed and the interrupt was applied to the next
instruction, meaning that SRR0 ended up pointing to the following
instruction.  To fix this, when an access causing an alignment
interrupt is going into r2, we set r2.busy for one cycle and set
r2.one_cycle to 0 so that the complete signal doesn't get asserted.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2 weeks ago
.github/workflows ci: Use newer version of actions/upload-artifact (#433) 1 month ago
constraints ECPIX-5: Add liteeth support 10 months ago
fpga Implement CTRL register 1 month ago
hello_world
include Merge pull request #404 from CodeConstruct:dev/gpio-interrupt 1 year ago
lib
litedram ECPIX-5: Add litedram support 10 months ago
liteeth ECPIX-5: Add liteeth support 10 months ago
litesdcard ECPIX-5: Add litesdcard support 10 months ago
media
micropython
openocd ECPIX-5: Add basic support 10 months ago
rust_lib_demo
scripts Implement cfuged, pdepd and pextd 1 month ago
sim-unisim
tests tests/trace: Add a couple of tests of CIABR function 2 weeks ago
uart16550 Bundle the uart16550 core file 2 years ago
verilator
.gitignore
LICENSE
Makefile Implement cfuged, pdepd and pextd 1 month ago
README.md
bitsort.vhdl Implement cfuged, pdepd and pextd 1 month ago
cache_ram.vhdl
common.vhdl execute1: Implement CIABR 2 weeks ago
control.vhdl
core.vhdl core: Implement the PIR SPR 3 weeks ago
core_debug.vhdl execute1: Make CFAR able to be written using mtspr and read using DMI debug 1 month ago
core_dram_tb.vhdl Move alt_reset to syscon 2 years ago
core_flash_tb.vhdl
core_tb.vhdl
countbits.vhdl Xilinx FPGAs: Eliminate Vivado critical warnings 10 months ago
countbits_tb.vhdl
cr_file.vhdl
crhelpers.vhdl
dcache.vhdl dcache: Improve timing 4 weeks ago
dcache_tb.vhdl Fix dcache_tb (and add dump of victim way to dcache) 2 years ago
decode1.vhdl execute1: Implement CIABR 2 weeks ago
decode2.vhdl Reimplement quadword loads and stores 1 month ago
decode_types.vhdl dcache: Implement data cache touch and flush instructions 1 month ago
divider.vhdl
divider_tb.vhdl
dmi_dtm_dummy.vhdl
dmi_dtm_ecp5.vhdl
dmi_dtm_tb.vhdl
dmi_dtm_xilinx.vhdl
dram_tb.vhdl Move alt_reset to syscon 2 years ago
execute1.vhdl execute1: Implement CIABR 2 weeks ago
fetch1.vhdl Implement scv and rfscv 1 month ago
foreign_random.vhdl
fpu.vhdl FPU: Fix ftdiv and ftsqrt instructions 10 months ago
git.vhdl.in
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glibc_random_helpers.vhdl
gpio.vhdl gpio: Add interrupts and trigger registers 2 years ago
helpers.vhdl
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icache_tb.vhdl icache_tb: Update for recent icache changes 1 year ago
icache_test.bin
insn_helpers.vhdl Decode prefixed instructions 2 years ago
loadstore1.vhdl loadstore1: Fix setting of SRR0 on alignment interrupt 2 weeks ago
logical.vhdl Implement byte reversal instructions 1 year ago
microwatt.core Implement cfuged, pdepd and pextd 1 month ago
mmu.vhdl Move iTLB from icache to fetch1 1 year ago
multiply-32s.vhdl
multiply.vhdl
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nonrandom.vhdl
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plrufn.vhdl
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predecode.vhdl Reimplement quadword loads and stores 1 month ago
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rotator.vhdl
rotator_tb.vhdl
run.py Fix compatibility with latest VUnit release 1 year ago
sim_16550_uart.vhdl
sim_bram.vhdl
sim_bram_helpers.vhdl
sim_bram_helpers_c.c
sim_console.vhdl
sim_console_c.c
sim_jtag.vhdl
sim_jtag_socket.vhdl
sim_jtag_socket_c.c
sim_no_flash.vhdl
sim_pp_uart.vhdl
sim_vhpi_c.c
sim_vhpi_c.h
soc.vhdl core: Implement the PIR SPR 3 weeks ago
spi_flash_ctrl.vhdl
spi_rxtx.vhdl
sync_fifo.vhdl
syscon.vhdl Move alt_reset to syscon 2 years ago
utils.vhdl
wishbone_arbiter.vhdl
wishbone_bram_tb.bin
wishbone_bram_tb.vhdl
wishbone_bram_wrapper.vhdl
wishbone_debug_master.vhdl
wishbone_types.vhdl
writeback.vhdl Implement scv and rfscv 1 month ago
xics.vhdl Xilinx FPGAs: Eliminate Vivado critical warnings 10 months ago
xilinx-mult-32s.vhdl Xilinx FPGAs: Eliminate Vivado critical warnings 10 months ago
xilinx-mult.vhdl

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • If this is your first time using fusesoc, initialize fusesoc. This is needed to be able to pull down fussoc library components referenced by microwatt. Run
fusesoc init
fusesoc fetch uart16550
fusesoc library add microwatt /path/to/microwatt
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100): You may wish to ensure you have installed Digilent Board files or appropriate files for your board first.
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Linux on Microwatt

Mainline Linux supports Microwatt as of v5.14. The Arty A7 is the best tested platform, but it's also been tested on the OrangeCrab and ButterStick.

  1. Use buildroot to create a userspace

    A small change is required to glibc in order to support the VMX/AltiVec-less Microwatt, as float128 support is mandiatory and for this in GCC requires VSX/AltiVec. This change is included in Joel's buildroot fork, along with a defconfig:

    git clone -b microwatt https://github.com/shenki/buildroot
    cd buildroot
    make ppc64le_microwatt_defconfig
    make
    

    The output is output/images/rootfs.cpio.

  2. Build the Linux kernel

    git clone https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
    cd linux
    make ARCH=powerpc microwatt_defconfig
    make ARCH=powerpc CROSS_COMPILE=powerpc64le-linux-gnu- \
      CONFIG_INITRAMFS_SOURCE=/buildroot/output/images/rootfs.cpio -j`nproc`
    

    The output is arch/powerpc/boot/dtbImage.microwatt.elf.

  3. Build gateware using FuseSoC

    First configure FuseSoC as above.

    fusesoc run --build --target=arty_a7-100 microwatt --no_bram --memory_size=0
    

    The output is build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit.

  4. Program the flash

    This operation will overwrite the contents of your flash.

    For the Arty A7 A100, set FLASH_ADDRESS to 0x400000 and pass -f a100.

    For the Arty A7 A35, set FLASH_ADDRESS to 0x300000 and pass -f a35.

    microwatt/openocd/flash-arty -f a100 build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit
    microwatt/openocd/flash-arty -f a100 dtbImage.microwatt.elf -t bin -a $FLASH_ADDRESS
    
  5. Connect to the second USB TTY device exposed by the FPGA

    minicom -D /dev/ttyUSB1
    

    The gateware has firmware that will look at FLASH_ADDRESS and attempt to parse an ELF there, loading it to the address specified in the ELF header and jumping to it.

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

  • There are a few instructions still to be implemented:
    • Vector/VMX/VSX