forked from cores/microwatt
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64 Commits
Author | SHA1 | Date |
---|---|---|
Paul Mackerras | 35e0dbed34 | 2 years ago |
Michael Neuling | cd52390bf1 | 2 years ago |
Michael Neuling | b983d5080e | 2 years ago |
Michael Neuling | d4db331467 | 2 years ago |
Michael Neuling | ee5e3778ed | 2 years ago |
Michael Neuling | c43692f4c7 | 2 years ago |
Michael Neuling | 956df2c863 | 2 years ago |
Michael Neuling | 3627f102db | 2 years ago |
Paul Mackerras | 6e1e763c02 | 2 years ago |
Anton Blanchard | 1047239a37 | 2 years ago |
Anton Blanchard | 9d35340bb1 | 2 years ago |
Michael Neuling | b82eea5933 | 2 years ago |
Anton Blanchard | d3aff67fa7 | 2 years ago |
Anton Blanchard | b47b71821e | 2 years ago |
Anton Blanchard | 71d4b5ed20 | 2 years ago |
Anton Blanchard | a527d9b959 | 2 years ago |
Anton Blanchard | e7f0a7c7ac | 2 years ago |
Anton Blanchard | 39220be311 | 2 years ago |
Anton Blanchard | 843361f2be | 2 years ago |
Anton Blanchard | d3a7517318 | 2 years ago |
Anton Blanchard | 1ff852b012 | 2 years ago |
Anton Blanchard | e2438071a1 | 2 years ago |
Anton Blanchard | b7c4d3c5c3 | 2 years ago |
Anton Blanchard | f06abb67ad | 2 years ago |
Anton Blanchard | 64d2def0c6 | 2 years ago |
Anton Blanchard | ff442d1bdb | 2 years ago |
Anton Blanchard | b8fc5636a4 | 2 years ago |
Anton Blanchard | ebdddcc402 | 2 years ago |
Anton Blanchard | a750365ffa | 2 years ago |
Joel Stanley | 9ec22af256 | 2 years ago |
Joel Stanley | a31725d989 | 2 years ago |
Michael Neuling | f5e06c2d4b | 2 years ago |
Anton Blanchard | 948f6f43a7 | 2 years ago |
Michael Neuling | 8bf48ac094 | 2 years ago |
Anton Blanchard | b5accb78b2 | 2 years ago |
Michael Neuling | 30fd936c12 | 2 years ago |
Michael Neuling | af1b76d944 | 2 years ago |
Michael Neuling | 9b96ab730c | 2 years ago |
Anton Blanchard | 0b39947f8d | 2 years ago |
Anton Blanchard | 00bf0af21c | 2 years ago |
Anton Blanchard | 50b4cb9423 | 2 years ago |
Tianrui Wei | 844ca0e6b5 | 2 years ago |
Michael Neuling | f01f3d233a | 2 years ago |
Matt Johnston | c0c00d05bc | 2 years ago |
Michael Neuling | ffcdaaa92d | 2 years ago |
Michael Neuling | b4770197a2 | 2 years ago |
Raptor Engineering Development Team | fcb783a0fb | 2 years ago |
Michael Neuling | 2b97fb0bf3 | 2 years ago |
Paul Mackerras | 0aa898c7a6 | 2 years ago |
Paul Mackerras | 1720a0584a | 2 years ago |
Paul Mackerras | 1086988883 | 2 years ago |
Paul Mackerras | 4cf2921b0b | 2 years ago |
Michael Neuling | 27b660ef76 | 2 years ago |
Anton Blanchard | 5a5a082601 | 2 years ago |
Matt Johnston | 9c64f8a98b | 2 years ago |
Matt Johnston | 3775650df3 | 2 years ago |
Matt Johnston | eb20195a10 | 2 years ago |
Matt Johnston | 763138798e | 2 years ago |
Matt Johnston | 04cc4a842c | 2 years ago |
Matt Johnston | e05ae0c8cb | 2 years ago |
Paul Mackerras | 49ec80ac3e | 2 years ago |
Paul Mackerras | cef3660e74 | 2 years ago |
Paul Mackerras | 2491aa7fc5 | 2 years ago |
Michael Neuling | 286757f0f7 | 2 years ago |
@ -0,0 +1,136 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.helpers.all;
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entity bit_counter is
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port (
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clk : in std_logic;
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rs : in std_ulogic_vector(63 downto 0);
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count_right : in std_ulogic;
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do_popcnt : in std_ulogic;
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is_32bit : in std_ulogic;
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datalen : in std_ulogic_vector(3 downto 0);
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result : out std_ulogic_vector(63 downto 0)
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);
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end entity bit_counter;
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architecture behaviour of bit_counter is
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-- signals for count-leading/trailing-zeroes
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signal inp : std_ulogic_vector(63 downto 0);
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signal inp_r : std_ulogic_vector(63 downto 0);
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signal sum : std_ulogic_vector(64 downto 0);
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signal sum_r : std_ulogic_vector(64 downto 0);
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signal onehot : std_ulogic_vector(63 downto 0);
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signal edge : std_ulogic_vector(63 downto 0);
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signal bitnum : std_ulogic_vector(5 downto 0);
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signal cntz : std_ulogic_vector(63 downto 0);
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-- signals for popcnt
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signal dlen_r : std_ulogic_vector(3 downto 0);
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signal pcnt_r : std_ulogic;
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subtype twobit is unsigned(1 downto 0);
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type twobit32 is array(0 to 31) of twobit;
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signal pc2 : twobit32;
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subtype threebit is unsigned(2 downto 0);
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type threebit16 is array(0 to 15) of threebit;
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signal pc4 : threebit16;
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subtype fourbit is unsigned(3 downto 0);
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type fourbit8 is array(0 to 7) of fourbit;
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signal pc8 : fourbit8;
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signal pc8_r : fourbit8;
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subtype sixbit is unsigned(5 downto 0);
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type sixbit2 is array(0 to 1) of sixbit;
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signal pc32 : sixbit2;
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signal popcnt : std_ulogic_vector(63 downto 0);
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begin
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countzero_r: process(clk)
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begin
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if rising_edge(clk) then
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inp_r <= inp;
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sum_r <= sum;
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end if;
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end process;
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countzero: process(all)
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variable bitnum_e, bitnum_o : std_ulogic_vector(5 downto 0);
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begin
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if is_32bit = '0' then
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if count_right = '0' then
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inp <= bit_reverse(rs);
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else
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inp <= rs;
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end if;
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else
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inp(63 downto 32) <= x"FFFFFFFF";
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if count_right = '0' then
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inp(31 downto 0) <= bit_reverse(rs(31 downto 0));
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else
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inp(31 downto 0) <= rs(31 downto 0);
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end if;
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end if;
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sum <= std_ulogic_vector(unsigned('0' & not inp) + 1);
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-- The following occurs after a clock edge
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edge <= sum_r(63 downto 0) or inp_r;
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bitnum_e := edgelocation(edge, 6);
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onehot <= sum_r(63 downto 0) and inp_r;
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bitnum_o := bit_number(onehot);
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bitnum(5 downto 2) <= bitnum_e(5 downto 2);
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bitnum(1 downto 0) <= bitnum_o(1 downto 0);
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cntz <= 57x"0" & sum_r(64) & bitnum;
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end process;
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popcnt_r: process(clk)
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begin
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if rising_edge(clk) then
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for i in 0 to 7 loop
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pc8_r(i) <= pc8(i);
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end loop;
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dlen_r <= datalen;
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pcnt_r <= do_popcnt;
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end if;
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end process;
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popcnt_a: process(all)
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begin
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for i in 0 to 31 loop
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pc2(i) <= unsigned("0" & rs(i * 2 downto i * 2)) + unsigned("0" & rs(i * 2 + 1 downto i * 2 + 1));
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end loop;
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for i in 0 to 15 loop
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pc4(i) <= ('0' & pc2(i * 2)) + ('0' & pc2(i * 2 + 1));
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end loop;
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for i in 0 to 7 loop
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pc8(i) <= ('0' & pc4(i * 2)) + ('0' & pc4(i * 2 + 1));
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end loop;
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-- after a clock edge
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for i in 0 to 1 loop
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pc32(i) <= ("00" & pc8_r(i * 4)) + ("00" & pc8_r(i * 4 + 1)) +
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("00" & pc8_r(i * 4 + 2)) + ("00" & pc8_r(i * 4 + 3));
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end loop;
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popcnt <= (others => '0');
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if dlen_r(3 downto 2) = "00" then
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-- popcntb
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for i in 0 to 7 loop
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popcnt(i * 8 + 3 downto i * 8) <= std_ulogic_vector(pc8_r(i));
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end loop;
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elsif dlen_r(3) = '0' then
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-- popcntw
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for i in 0 to 1 loop
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popcnt(i * 32 + 5 downto i * 32) <= std_ulogic_vector(pc32(i));
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end loop;
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else
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popcnt(6 downto 0) <= std_ulogic_vector(('0' & pc32(0)) + ('0' & pc32(1)));
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end if;
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end process;
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result <= cntz when pcnt_r = '0' else popcnt;
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end behaviour;
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@ -1,60 +0,0 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.helpers.all;
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entity zero_counter is
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port (
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clk : in std_logic;
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rs : in std_ulogic_vector(63 downto 0);
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count_right : in std_ulogic;
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is_32bit : in std_ulogic;
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result : out std_ulogic_vector(63 downto 0)
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);
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end entity zero_counter;
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architecture behaviour of zero_counter is
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signal inp : std_ulogic_vector(63 downto 0);
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signal sum : std_ulogic_vector(64 downto 0);
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signal msb_r : std_ulogic;
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signal onehot : std_ulogic_vector(63 downto 0);
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signal onehot_r : std_ulogic_vector(63 downto 0);
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signal bitnum : std_ulogic_vector(5 downto 0);
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begin
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countzero_r: process(clk)
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begin
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if rising_edge(clk) then
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msb_r <= sum(64);
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onehot_r <= onehot;
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end if;
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end process;
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countzero: process(all)
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begin
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if is_32bit = '0' then
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if count_right = '0' then
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inp <= bit_reverse(rs);
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else
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inp <= rs;
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end if;
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else
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inp(63 downto 32) <= x"FFFFFFFF";
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if count_right = '0' then
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inp(31 downto 0) <= bit_reverse(rs(31 downto 0));
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else
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inp(31 downto 0) <= rs(31 downto 0);
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end if;
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end if;
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sum <= std_ulogic_vector(unsigned('0' & not inp) + 1);
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onehot <= sum(63 downto 0) and inp;
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-- The following occurs after a clock edge
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bitnum <= bit_number(onehot_r);
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result <= x"00000000000000" & "0" & msb_r & bitnum;
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end process;
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end behaviour;
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@ -0,0 +1,298 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.math_real.all;
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library work;
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use work.wishbone_types.all;
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entity dmi_dtm is
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generic(ABITS : INTEGER:=8;
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DBITS : INTEGER:=64);
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port(sys_clk : in std_ulogic;
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sys_reset : in std_ulogic;
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dmi_addr : out std_ulogic_vector(ABITS - 1 downto 0);
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dmi_din : in std_ulogic_vector(DBITS - 1 downto 0);
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dmi_dout : out std_ulogic_vector(DBITS - 1 downto 0);
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dmi_req : out std_ulogic;
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dmi_wr : out std_ulogic;
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dmi_ack : in std_ulogic
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-- dmi_err : in std_ulogic TODO: Add error response
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);
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end entity dmi_dtm;
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architecture behaviour of dmi_dtm is
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-- Signals coming out of the JTAGG block
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signal jtag_reset_n : std_ulogic;
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signal tdi : std_ulogic;
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signal tdo : std_ulogic;
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signal tck : std_ulogic;
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signal jce1 : std_ulogic;
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signal jshift : std_ulogic;
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signal update : std_ulogic;
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-- signals to match dmi_dtb_xilinx
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signal jtag_reset : std_ulogic;
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signal capture : std_ulogic;
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signal jtag_clk : std_ulogic;
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signal sel : std_ulogic;
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signal shift : std_ulogic;
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-- delays
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signal jce1_d : std_ulogic;
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constant TCK_DELAY : INTEGER := 8;
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signal tck_d : std_ulogic_vector(TCK_DELAY+1 downto 1);
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-- ** JTAG clock domain **
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-- Shift register
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signal shiftr : std_ulogic_vector(ABITS + DBITS + 1 downto 0);
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-- Latched request
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signal request : std_ulogic_vector(ABITS + DBITS + 1 downto 0);
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-- A request is present
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signal jtag_req : std_ulogic;
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-- Synchronizer for jtag_rsp (sys clk -> jtag_clk)
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signal dmi_ack_0 : std_ulogic;
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signal dmi_ack_1 : std_ulogic;
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-- ** sys clock domain **
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-- Synchronizer for jtag_req (jtag clk -> sys clk)
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signal jtag_req_0 : std_ulogic;
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signal jtag_req_1 : std_ulogic;
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-- ** combination signals
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signal jtag_bsy : std_ulogic;
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signal op_valid : std_ulogic;
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signal rsp_op : std_ulogic_vector(1 downto 0);
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-- ** Constants **
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constant DMI_REQ_NOP : std_ulogic_vector(1 downto 0) := "00";
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constant DMI_REQ_RD : std_ulogic_vector(1 downto 0) := "01";
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constant DMI_REQ_WR : std_ulogic_vector(1 downto 0) := "10";
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constant DMI_RSP_OK : std_ulogic_vector(1 downto 0) := "00";
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constant DMI_RSP_BSY : std_ulogic_vector(1 downto 0) := "11";
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attribute ASYNC_REG : string;
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attribute ASYNC_REG of jtag_req_0: signal is "TRUE";
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attribute ASYNC_REG of jtag_req_1: signal is "TRUE";
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attribute ASYNC_REG of dmi_ack_0: signal is "TRUE";
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attribute ASYNC_REG of dmi_ack_1: signal is "TRUE";
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-- ECP5 JTAGG
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component JTAGG is
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generic (
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ER1 : string := "ENABLED";
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ER2 : string := "ENABLED"
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);
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port(
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JTDO1 : in std_ulogic;
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JTDO2 : in std_ulogic;
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JTDI : out std_ulogic;
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JTCK : out std_ulogic;
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JRTI1 : out std_ulogic;
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JRTI2 : out std_ulogic;
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JSHIFT : out std_ulogic;
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JUPDATE : out std_ulogic;
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JRSTN : out std_ulogic;
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JCE1 : out std_ulogic;
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JCE2 : out std_ulogic
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);
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end component;
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component LUT4 is
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generic (
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INIT : std_logic_vector
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);
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port(
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A : in STD_ULOGIC;
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B : in STD_ULOGIC;
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||||
C : in STD_ULOGIC;
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D : in STD_ULOGIC;
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Z : out STD_ULOGIC
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);
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end component;
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begin
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jtag: JTAGG
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generic map(
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ER2 => "DISABLED"
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)
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port map (
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JTDO1 => tdo,
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JTDO2 => '0',
|
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JTDI => tdi,
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JTCK => tck,
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JRTI1 => open,
|
||||
JRTI2 => open,
|
||||
JSHIFT => jshift,
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||||
JUPDATE => update,
|
||||
JRSTN => jtag_reset_n,
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||||
JCE1 => jce1,
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||||
JCE2 => open
|
||||
);
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||||
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||||
-- JRTI1 looks like it could be connected to SEL, but
|
||||
-- in practise JRTI1 is only high briefly, not for the duration
|
||||
-- of the transmission. possibly mw_debug could be modified.
|
||||
-- The ecp5 is probably the only jtag device anyway.
|
||||
sel <= '1';
|
||||
|
||||
-- TDI needs to align with TCK, we use LUT delays here.
|
||||
-- From https://github.com/enjoy-digital/litex/pull/1087
|
||||
tck_d(1) <= tck;
|
||||
del: for i in 1 to TCK_DELAY generate
|
||||
attribute keep : boolean;
|
||||
attribute keep of l: label is true;
|
||||
begin
|
||||
l: LUT4
|
||||
generic map(
|
||||
INIT => b"0000_0000_0000_0010"
|
||||
)
|
||||
port map (
|
||||
A => tck_d(i),
|
||||
B => '0', C => '0', D => '0',
|
||||
Z => tck_d(i+1)
|
||||
);
|
||||
end generate;
|
||||
jtag_clk <= tck_d(TCK_DELAY+1);
|
||||
|
||||
-- capture signal
|
||||
jce1_sync : process(jtag_clk)
|
||||
begin
|
||||
if rising_edge(jtag_clk) then
|
||||
jce1_d <= jce1;
|
||||
capture <= jce1 and not jce1_d;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- latch the shift signal, otherwise
|
||||
-- we miss the last shift in
|
||||
-- (maybe because we are delaying tck?)
|
||||
shift_sync : process(jtag_clk)
|
||||
begin
|
||||
if (sys_reset = '1') then
|
||||
shift <= '0';
|
||||
elsif rising_edge(jtag_clk) then
|
||||
shift <= jshift;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
jtag_reset <= not jtag_reset_n;
|
||||
|
||||
-- dmi_req synchronization
|
||||
dmi_req_sync : process(sys_clk)
|
||||
begin
|
||||
-- sys_reset is synchronous
|
||||
if rising_edge(sys_clk) then
|
||||
if (sys_reset = '1') then
|
||||
jtag_req_0 <= '0';
|
||||
jtag_req_1 <= '0';
|
||||
else
|
||||
jtag_req_0 <= jtag_req;
|
||||
jtag_req_1 <= jtag_req_0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
dmi_req <= jtag_req_1;
|
||||
|
||||
-- dmi_ack synchronization
|
||||
dmi_ack_sync: process(jtag_clk, jtag_reset)
|
||||
begin
|
||||
-- jtag_reset is async (see comments)
|
||||
if jtag_reset = '1' then
|
||||
dmi_ack_0 <= '0';
|
||||
dmi_ack_1 <= '0';
|
||||
elsif rising_edge(jtag_clk) then
|
||||
dmi_ack_0 <= dmi_ack;
|
||||
dmi_ack_1 <= dmi_ack_0;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- jtag_bsy indicates whether we can start a new request, we can when
|
||||
-- we aren't already processing one (jtag_req) and the synchronized ack
|
||||
-- of the previous one is 0.
|
||||
--
|
||||
jtag_bsy <= jtag_req or dmi_ack_1;
|
||||
|
||||
-- decode request type in shift register
|
||||
with shiftr(1 downto 0) select op_valid <=
|
||||
'1' when DMI_REQ_RD,
|
||||
'1' when DMI_REQ_WR,
|
||||
'0' when others;
|
||||
|
||||
-- encode response op
|
||||
rsp_op <= DMI_RSP_BSY when jtag_bsy = '1' else DMI_RSP_OK;
|
||||
|
||||
-- Some DMI out signals are directly driven from the request register
|
||||
dmi_addr <= request(ABITS + DBITS + 1 downto DBITS + 2);
|
||||
dmi_dout <= request(DBITS + 1 downto 2);
|
||||
dmi_wr <= '1' when request(1 downto 0) = DMI_REQ_WR else '0';
|
||||
|
||||
-- TDO is wired to shift register bit 0
|
||||
tdo <= shiftr(0);
|
||||
|
||||
-- Main state machine. Handles shift registers, request latch and
|
||||
-- jtag_req latch. Could be split into 3 processes but it's probably
|
||||
-- not worthwhile.
|
||||
--
|
||||
shifter: process(jtag_clk, jtag_reset, sys_reset)
|
||||
begin
|
||||
if jtag_reset = '1' or sys_reset = '1' then
|
||||
shiftr <= (others => '0');
|
||||
jtag_req <= '0';
|
||||
request <= (others => '0');
|
||||
elsif rising_edge(jtag_clk) then
|
||||
|
||||
-- Handle jtag "commands" when sel is 1
|
||||
if sel = '1' then
|
||||
-- Shift state, rotate the register
|
||||
if shift = '1' then
|
||||
shiftr <= tdi & shiftr(ABITS + DBITS + 1 downto 1);
|
||||
end if;
|
||||
|
||||
-- Update state (trigger)
|
||||
--
|
||||
-- Latch the request if we aren't already processing one and
|
||||
-- it has a valid command opcode.
|
||||
--
|
||||
if update = '1' and op_valid = '1' then
|
||||
if jtag_bsy = '0' then
|
||||
request <= shiftr;
|
||||
jtag_req <= '1';
|
||||
end if;
|
||||
-- Set the shift register "op" to "busy". This will prevent
|
||||
-- us from re-starting the command on the next update if
|
||||
-- the command completes before that.
|
||||
shiftr(1 downto 0) <= DMI_RSP_BSY;
|
||||
end if;
|
||||
|
||||
-- Request completion.
|
||||
--
|
||||
-- Capture the response data for reads and clear request flag.
|
||||
--
|
||||
-- Note: We clear req (and thus dmi_req) here which relies on tck
|
||||
-- ticking and sel set. This means we are stuck with dmi_req up if
|
||||
-- the jtag interface stops. Slaves must be resilient to this.
|
||||
--
|
||||
if jtag_req = '1' and dmi_ack_1 = '1' then
|
||||
jtag_req <= '0';
|
||||
if request(1 downto 0) = DMI_REQ_RD then
|
||||
request(DBITS + 1 downto 2) <= dmi_din;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Capture state, grab latch content with updated status
|
||||
if capture = '1' then
|
||||
shiftr <= request(ABITS + DBITS + 1 downto 2) & rsp_op;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end architecture behaviour;
|
||||
|
Binary file not shown.
Binary file not shown.
@ -1,13 +1,27 @@
|
||||
SECTIONS
|
||||
{
|
||||
_start = .;
|
||||
. = 0;
|
||||
_start = .;
|
||||
.head : {
|
||||
KEEP(*(.head))
|
||||
}
|
||||
}
|
||||
. = 0x1000;
|
||||
.text : { *(.text) }
|
||||
.text : { *(.text) *(.text.*) *(.rodata) *(.rodata.*) }
|
||||
. = 0x1800;
|
||||
.data : { *(.data) }
|
||||
.bss : { *(.bss) }
|
||||
.data : { *(.data) *(.data.*) *(.got) *(.toc) }
|
||||
. = ALIGN(0x80);
|
||||
__bss_start = .;
|
||||
.bss : {
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.common)
|
||||
*(.bss.*)
|
||||
}
|
||||
. = ALIGN(0x80);
|
||||
__bss_end = .;
|
||||
. = . + 0x2000;
|
||||
__stack_top = .;
|
||||
}
|
||||
|
Loading…
Reference in New Issue