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187199c489 Remove -waveform from xdc files Anton Blanchard 2021-08-09 13:02:01 +1000
7994b98404 Fix some whitespace issues Anton Blanchard 2021-08-09 06:44:43 +1000
46cde3bb23

Merge pull request #305 from mikey/noflatten Anton Blanchard 2021-08-09 11:28:49 +1000
780d6c754c litedram: Regenerate from upstream litex Anton Blanchard 2021-08-09 10:54:35 +1000
07f2edc415 litedram: sdrinit() is now sdram_init() Anton Blanchard 2021-08-09 10:53:51 +1000
346686feb8 litedram: Fix compiler warning Anton Blanchard 2021-08-09 10:29:48 +1000
ac546a3024 litedram: Update yaml files Anton Blanchard 2021-08-09 10:26:35 +1000
6034a9e31f litedram: simplify generate.py Anton Blanchard 2021-08-09 10:24:38 +1000
3275304a7f litedram: Remove variables.mak Anton Blanchard 2021-08-09 09:49:03 +1000
d6efbb327f ci: Remove noflatten to reduce size of ECP5 builds Michael Neuling 2021-08-04 16:33:52 +1000
0199ff8ca8

Merge pull request #299 from mikey/vunit-make Anton Blanchard 2021-08-04 13:59:22 +1000
25ab1053e9

Merge pull request #304 from umarcor/ci-backends Michael Neuling 2021-08-04 09:57:35 +1000
de41dfc703 ci: test 'build' with LLVM and GCC backends umarcor 2021-07-22 00:02:41 +0200
0cd826d190

Merge pull request #301 from umarcor/vunit-cleanup Michael Neuling 2021-08-02 14:22:11 +1000
bf76261979 makefile: Add check_vunit Michael Neuling 2021-06-21 11:35:56 +1000
178c2a7da3 VUnit: style umarcor 2021-07-21 19:54:27 +0200
2031c6d2d2 VUnit: use Path.glob instead of glob.glob umarcor 2021-07-21 19:52:24 +0200
7571416f81 ci: add 'workflow_dispatch' umarcor 2021-07-21 18:09:37 +0200
faf8309629 ci: in job 'VUnit' use a container step instead of a container job umarcor 2021-07-21 18:04:15 +0200
d7458d5beb

Reduce the size of icache to help yosys ECP5 builds (#303) Michael Neuling 2021-07-31 11:18:39 +1000
f9654428ff

Merge pull request #296 from LarsAsplund/logging-checking Michael Neuling 2021-06-21 17:58:34 +1000
9e3c756234

Merge pull request #298 from paulusmack/master Michael Neuling 2021-06-21 11:51:13 +1000
ff7421c54e

Merge pull request #295 from LarsAsplund/master Michael Neuling 2021-06-21 11:25:40 +1000
18120f153d MMU: Implement a vestigial partition table Paul Mackerras 2021-06-17 20:01:32 +1000
478b787c10 Replaced VHDL assert and report with VUnit checking and logging Lars Asplund 2021-06-09 23:50:02 +0200
0865704e21 Run VUnit tests in CI Lars Asplund 2021-06-09 16:19:24 +0200
0940b8a9d3 Organized VUnit testbenches into test cases. Lars Asplund 2021-06-08 22:32:57 +0200
08c0c4c1b4 Make core testbenches recognized by VUnit Lars Asplund 2021-06-07 22:34:00 +0200
41d57e6148 Added VUnit run script. Lars Asplund 2021-06-07 22:05:57 +0200
84473eda1b Merge pull request #277 from paulus/gpio Michael Neuling 2021-05-17 16:19:47 +1000
7f44980611

Merge pull request #287 from paulusmack/master Michael Neuling 2021-05-14 09:11:41 +1000
d8ea64675a

Merge pull request #278 from shenki/openocd-v0.11 Paul Mackerras 2021-05-11 20:25:29 +1000
0d4a0bab6e openocd: Fix verify command for v0.10 Joel Stanley 2021-05-11 14:17:26 +0930
21ed730514 arty_a7: Add litesdcard interface Paul Mackerras 2021-04-15 17:22:31 +1000
231003f7c7 icache: Snoop writes to memory by other agents Paul Mackerras 2021-05-11 14:04:08 +1000
4c11c9c661 dcache: Simplify logic in RELOAD_WAIT_ACK state Paul Mackerras 2021-05-11 11:29:46 +1000
eb7eba2d92 dcache: Snoop writes to memory by other agents Paul Mackerras 2021-05-11 10:54:57 +1000
4a8ab3331c

Merge pull request #283 from antonblanchard/whitespace Paul Mackerras 2021-05-05 10:20:46 +1000
d9a398dc81

Update documentation. (#280) Antony Vennard 2021-05-05 02:15:26 +0200
6d827b9358

Merge pull request #286 from antonblanchard/Makefile-cleanup-3 Anton Blanchard 2021-03-25 14:43:45 +1100
be11ebbf6d Remove unused GHDL_TARGET_GENERICS Anton Blanchard 2021-03-25 14:05:00 +1100
33c78f9282 Move verilator --trace flag into VERILATOR_FLAGS Anton Blanchard 2021-03-24 21:40:26 +1100
0af906232f

Merge pull request #285 from antonblanchard/Makefile-cleanup-2 Anton Blanchard 2021-03-24 21:31:54 +1100
5cc5d8f030

Merge pull request #281 from antonblanchard/cache-tlb-parameters Anton Blanchard 2021-03-24 20:44:45 +1100
4ab36517ec Remove -frelaxed Anton Blanchard 2021-03-24 17:08:29 +1100
561d6af6f0 Use VERILATOR_FLAGS/VERILATOR_CFLAGS on all verilator targets Anton Blanchard 2021-03-24 17:07:56 +1100
75da4156fe Remove core_files from soc_files and fpga_files Anton Blanchard 2021-03-24 15:08:18 +1100
ef01fa32bd

Merge pull request #284 from antonblanchard/boot-clocks Anton Blanchard 2021-03-23 20:02:27 +1100
53ccf89d26 Use a record for cache parameters cache-tlb-parameters-2 Anton Blanchard 2021-03-23 10:32:25 +1100
af462f0ca9 Reformat spi_flash_ctrl Anton Blanchard 2021-03-22 11:01:10 +1100
2db89628ab Reformat control Anton Blanchard 2021-03-22 10:55:53 +1100
21f482f967 Reformat testbenches Anton Blanchard 2021-03-22 10:55:32 +1100
0d86580ac7 Reformat writeback Anton Blanchard 2021-03-22 10:19:27 +1100
f67b143165 Reformat plru Anton Blanchard 2021-03-22 10:17:49 +1100
c76e638a77 Reformat rotator Anton Blanchard 2021-03-22 10:09:39 +1100
601f3211be Reformat divider Anton Blanchard 2021-03-22 10:08:29 +1100
bf96279ff1 Reformat countzero Anton Blanchard 2021-03-22 10:07:47 +1100
af7e330d69 Reformat cr_file Anton Blanchard 2021-03-22 10:07:33 +1100
9208276aa2 Reformat register_file Anton Blanchard 2021-03-22 10:06:03 +1100
74254bf11a Reformat cache_ram Anton Blanchard 2021-03-22 09:56:12 +1100
91a53d8001 Allow SPI BOOT_CLOCKS to be overridden by top level Anton Blanchard 2021-03-15 20:03:45 +1100
2d21b95f87 Pass icache/dcache/tlb parameters down from soc Anton Blanchard 2021-03-15 18:18:21 +1100
f06a0f4e5a arty: Update GPIOs for Boxarty BMC Paul Mackerras 2021-03-09 13:16:28 +1100
24a34899b4 Add files for openocd v0.11 Joel Stanley 2021-02-17 17:09:47 +1030
f06ffcf9b7 Add a GPIO controller and use it to drive the shield I/O pins on the Arty Paul Mackerras 2021-02-23 21:44:04 +1100
6523acc743

Merge pull request #274 from mikey/read-sprs Michael Neuling 2021-02-09 10:06:03 +1100
d26a157cd7 Add a test to read from all SPRs Anton Blanchard 2021-01-04 14:16:06 +1100
4c21587c4d Fix DAR/DSISR reading before they are written Michael Neuling 2021-02-08 20:17:48 +1100
6c7689052d

Merge pull request #269 from paulusmack/pipeline Michael Neuling 2021-02-08 17:27:16 +1100
9a6a7e9fe5

Merge pull request #268 from paulusmack/btc Michael Neuling 2021-02-08 16:38:57 +1100
7652452367

Merge pull request #273 from antonblanchard/wishbone-checking Michael Neuling 2021-02-08 14:34:53 +1100
c4e3ade4ed

Merge pull request #267 from paulusmack/master Michael Neuling 2021-02-08 14:26:53 +1100
481f3cdfea Add some wishbone checking Anton Blanchard 2021-02-08 12:15:53 +1100
17fd069640 core: Allow multiple loadstore instructions to be in flight Paul Mackerras 2020-12-28 15:15:30 +1100
f583d088b7 loadstore: Convert to 3-stage pipeline Paul Mackerras 2020-11-07 20:50:58 +1100
f636bb7c39 dcache: Fix bugs in pipelined operation Paul Mackerras 2021-01-18 08:55:56 +1100
acb3d2d745 core: Send FPU interrupts to writeback rather than execute1 Paul Mackerras 2020-12-23 13:57:40 +1100
29221315e9 core: Send loadstore1 interrupts to writeback rather than execute1 Paul Mackerras 2020-12-23 12:27:22 +1100
3cd3449b4b core: Move redirect and interrupt delivery logic to writeback Paul Mackerras 2020-12-23 11:13:21 +1100
4fd8d9509c execute1: Move CR result to data path process Paul Mackerras 2020-11-27 17:41:39 +1100
d6ac43251a execute1: Move data-path logic out to a separate process Paul Mackerras 2020-11-26 22:10:30 +1100
ae2afeca5c core: Track CR hazards and bypasses using tags Paul Mackerras 2020-11-12 22:07:33 +1100
d290d2a9bb core: Restore bypass path from execute1 Paul Mackerras 2020-11-11 09:42:17 +1100
c0b45e153b core: Track GPR hazards using tags that propagate through the pipelines Paul Mackerras 2020-11-10 20:04:00 +1100
a1d7b54f76 core: Crack branches that update both CTR and LR Paul Mackerras 2020-11-11 22:10:38 +1100
4c61a71a62 core: Crack update-form loads into two internal ops Paul Mackerras 2020-11-11 18:11:04 +1100
0fb207be60 fetch1: Implement a simple branch target cache Paul Mackerras 2020-12-19 09:25:04 +1100
f7b855dfc3 execute1: Improve timing on comparisons Paul Mackerras 2020-09-28 14:04:08 +1000
b0510fd1bb core: Reorganize execute1 Paul Mackerras 2020-09-26 19:58:46 +1000
658feabfd4 core: Make result multiplexing explicit Paul Mackerras 2020-09-26 17:19:57 +1000
9ea1ab0215 execute1: Move branch adder after register Paul Mackerras 2020-12-16 20:41:08 +1100
cb1e3f6d70 decode1: Take an extra cycle for predicted branch redirects Paul Mackerras 2020-12-16 19:32:07 +1100
6427cab46f loadstore1/dcache: Send store data one cycle later Paul Mackerras 2020-10-31 13:48:58 +1100
d1f35705c0 loadstore1: Improve timing of data path from cache RAM to writeback Paul Mackerras 2020-09-28 14:02:03 +1000
54f89afab7 loadstore1: Decide on load formatting controls a cycle earlier Paul Mackerras 2020-09-21 11:41:46 +1000
c0f282b691 decode1: Implement tlbsync as a no-op Paul Mackerras 2020-10-10 14:34:01 +1100
d6134babc0 decode1: Implement obsolete dst, dstst, dss instructions as no-ops Paul Mackerras 2020-09-22 10:03:30 +1000
89a67a18d0 decode: Add a facility field to the instruction decode tables Paul Mackerras 2020-12-12 12:38:06 +1100
ec5730a75a tests: Add tests for lq/stq and lqarx/stqcx. Paul Mackerras 2020-09-14 18:21:27 +1000
4b2c23703c core: Implement quadword loads and stores Paul Mackerras 2020-09-12 20:35:03 +1000