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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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862 Commits (7ec66d47fe0abbe1ff568ceb9228fbb9b0cd909a)
 

Author SHA1 Message Date
Anton Blanchard 7ec66d47fe Add a script to post process the microwatt verilog for caravel 4 years ago
Jordan Niethe 901cccd7da Connect to the caravel logic analyzer 
This connects 32 read and 32 write bits to the caravel logic analyzer.

Thanks to Jordan for the original patch
 4 years ago
Anton Blanchard 4667af332e Disable debug log 4 years ago
Anton Blanchard a9a8bee920 No need to set HAS_FPU and LOG_LENGTH in Makefile 4 years ago
Anton Blanchard 84f24a4773 tie off wb_ext_io_out 4 years ago
Anton Blanchard 2e3668f840 SPI fixes, and remove reset controller and PLL 
We need to expose all the input, output and output enable SPI lines
in order to use QSPI.

Remove the reset controller and PLL, since we are driving these
directly from caravel.
 4 years ago
Michael Neuling c87b883a82 Set alt reset vector to the start of flash at 0xf0000000 and make it 
programmable externally (using carvel LA)
 4 years ago
Michael Neuling b3a52bf931 Add mc*.vhdl from: 
git@github.com:openpowerwtf/uw_fab.git
 4 years ago
Anton Blanchard 9747879643 Add a simple test case 
We use 2 32bit RAMs, so we need to split the test case into
two files.
 4 years ago
Anton Blanchard 26fa3eda69 Add RAM_512x64 4 years ago
Anton Blanchard 03e213a393 Disable second uart since we aren't using it 4 years ago
Anton Blanchard 6bc8b3e7ad Add a toplevel file for caravel 4 years ago
Anton Blanchard 776e3b4815 Disable BOOT_CLOCKS in flash controller 4 years ago
Anton Blanchard e8e3e9bd17 Reduce the core size 
- 256B 2 way icache and dcache
- 2 entry 2 way dTLB
- 4 entry direct mapped iTLB
- 8 entry debug log
- disable FPU
 4 years ago
Anton Blanchard ef2ee09d1f Cut down hello_world to fit in 4kB 4 years ago
Michael Neuling 104e8b8b2a Cleanup some 'U' state issues 
Signed-off-by: Michael Neuling <mikey@neuling.org>
 4 years ago
Anton Blanchard ffcd9c6989 Work around ghdl/yosys issue with direct mapped TLB 
Workaround from Tristan.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 47dae4e9d4 Update JTAG TAP controller for Microwatt 
Make a few changes to match what mw_debug expects:

- 6 byte instructions
- IDCODE at 001001
- microwatt debug at 000011

Also change IDCODE to be an IBM ID.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 6544dbe94c First pass at an external JTAG port 
The verilator simulation interface uses the remote_bitbang
protocol from openocd. I have a simple implementation for
urjtag too.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 3f1e2b3a4f
Merge pull request #265 from antonblanchard/another-spi-rxtx-reset-issu 
Fix another reset issue in spi_rxtx
 4 years ago
Anton Blanchard 75be7803b2
Merge pull request #264 from antonblanchard/reset-spi-txrx 
Reset cmd_ready_o in spi_txrx
 4 years ago
Anton Blanchard a0eb4eec17 Fix another reset issue in spi_rxtx 
counter was X state after reset, initialize it.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard bf9a446e3f Reset cmd_ready_o in spi_txrx 
Initialize bit_count so that cmd_ready_o isn't X state immediately
after reset.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 39c826aa46
Merge pull request #261 from antonblanchard/wishbone_layout 
Make wishbone_master_out and wb_io_master_out match
 4 years ago
Anton Blanchard ebe696affc
Merge pull request #260 from paulusmack/misc 
soc: Drive uart1_irq to 0 when we don't have UART1
 4 years ago
Anton Blanchard c6dfc19d89 Make wishbone_master_out and wb_io_master_out match 
This makes it easier to parse the records in verilog because they
are getting flattened into an array of bits by ghdl/yosys.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Paul Mackerras e41cb01bca fetch1: Fix debug stop 
The ability to stop the core using the debug interface has been broken
since commit bb4332b7e6b5 ("Remove fetch2 pipeline stage"), which
removed a statement that cleared the valid bit on instructions when
their stop_mark was 1.

Fix this by clearing r.req coming out of fetch1 when r.stop_mark = 1.
This has the effect of making i_out.valid be 0 from the icache.  We
also fix a bug in icache.vhdl where it was not honouring i_in.req when
use_previous = 1.

It turns out that the logic in fetch1.vhdl to handle stopping and
restarting was not correct, with the effect that stopping the core
would leave NIA pointing to the last instruction executed, not the
next instruction to be executed.  In fact the state machine is
unnecessary and the whole thing can be simplified enormously - we
need to increment NIA whenever stop_in = 0 in the previous cycle.

Fixes: bb4332b7e6b5 ("Remove fetch2 pipeline stage")
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 4 years ago
Paul Mackerras 97586e7e99 soc: Drive uart1_irq to 0 when we don't have UART1 
The tools complain about uart1_irq not being driven and not having a
default when HAS_UART1 is false.  This sets it to 0 in that case.

Fixes: 7575b1e0c2 ("uart: Import and hook up opencore 16550 compatible UART")
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 4 years ago
Michael Neuling d96ee21c39
Merge pull request #256 from antonblanchard/flash-reset 
Fix a few reset issues in flash controller
 4 years ago
Paul Mackerras f4831507b3
Merge pull request #257 from antonblanchard/nofpu-fix 
Fully initialize FPU buses when FPU is disabled
 4 years ago
Anton Blanchard c870040a20 Fix an issue in flash controller when BOOT_CLOCKS is false 
If BOOT_CLOCKS is false we currently get stuck in the flash
state machine. This patch from Ben fixes it.

Also fix an x state issue I see in icarus verilog where we need
to reset auto_state.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 659be2780f Fully initialize FPU buses when FPU is disabled 
Some of the bits in the FPU buses end up as z state. Yosys
flags them, so we may as well clean it up.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 7c8bc85e44 Fix a few reset issues in flash controller 
Our flash controller fails when simulating with iverilog. Looking
closer, both wb_stash and auto_last_addr are X state, and things
fall apart after they get used.

Initialise them both fixes the iverilog issue.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 081dc64d39
Merge pull request #255 from antonblanchard/log-length 
Add LOG_LENGTH to top-generic.vhdl
 4 years ago
Anton Blanchard 86bdfe6fd4
Merge pull request #254 from antonblanchard/fix-verilator 
Add verilator FPGA target
 4 years ago
Anton Blanchard 80cf489e96 Add LOG_LENGTH to top-generic.vhdl 
The other top level files allow LOG_LENGTH to be configured.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard df8e1ca2a7 Add verilator FPGA target 
Our Makefiles need some work, but for now create an FPGA target:

make FPGA_TARGET=verilator microwatt-verilator

ghdl and yosys can use containers using PODMAN=1 or DOCKER=1
options.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 62d5b16c66
Merge pull request #253 from antonblanchard/fix-verilator 
Fix verilator build
 4 years ago
Anton Blanchard 4bc5169f78 Fix verilator build 
yosys and verilator did not like us passing in the verilog and
exporting it again. Pass the source directly to verilator instead.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Michael Neuling 77c03e5d42
Merge pull request #252 from antonblanchard/hello-world-in-8k 
Reduce hello_world footprint to fit in 8kB
 4 years ago
Anton Blanchard 605010e33d Fix ghdl warning due to variable shadowing in icache 
Fix a couple of ghdl warnings:

icache.vhdl:387:21⚠️ declaration of "i" hides constant "i" [-Whide]
icache.vhdl:400:17⚠️ declaration of "i" hides constant "i" [-Whide]

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard bc4e6b7efe Reduce hello_world footprint to fit in 8kB 
When building with yosys we assume hello_world fits in 8kB. There's
enough free space that we can adjust the linker script to make it fit.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Michael Neuling 16da9b5ba7
Merge pull request #249 from paulusmack/master 
Sundry bug fixes, plus implement mtmsr
 4 years ago
Michael Neuling b60026e7c1
Merge pull request #250 from umarcor/containers 
makefile: update synthesis containers
 4 years ago
Michael Neuling d839037f0b
Merge pull request #251 from umarcor/ci/containers 
ci: use job.container
 4 years ago
umarcor 93b2987b19 ci: use job.container 
Signed-off-by: umarcor <unai.martinezcorral@ehu.eus>
 4 years ago
umarcor de808d7a6a makefile: update synthesis containers 
Signed-off-by: umarcor <unai.martinezcorral@ehu.eus>
 4 years ago
umarcor d05737833e makefile: whitespace cleanup 
Signed-off-by: umarcor <unai.martinezcorral@ehu.eus>
 4 years ago
Paul Mackerras 29fabeb12e tests/misc: Add a test for correct CTR and LR updating by branches 
This adds a test with a bdnzl followed immediately by a bdnz, to check
that CTR and LR both get evaluated and written back correctly in this
situation.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 4 years ago
Paul Mackerras e49192cb5b execute1: Fix forwarding of result when doing delayed LR update 
Random execution testcases showed that a bdnzl which doesn't branch,
followed immediately by a bdnz, uses the wrong value for CTR for the
bdnz.  Decode2 detects the read-after-write hazard on CTR and tells
execute1 to use the bypass path.  However, the bdnzl takes two cycles
because it has to write back both CTR and LR, meaning that by the time
the bdnz starts to execute, r.e.write_data no longer contains the CTR
value, but instead contains zero.

To fix this, we make execute1 maintain the written-back value of CTR
in r.e.write_data across the cycle where LR is written back (this is
possible because the LR writeback uses the exc_write_data path).

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 4 years ago